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Problem generating the ddr2 UniPhy

mjdale2003
Beginner
174 Views

I am having a problem generating the ddr2 UniPhy, it keeps reporting an error.

searching the forums this has been addressed many times before but none of the fixes seem to work. I have tried all the combinations of

wsl1 and wsl2 

enabled and disabled Windows subsystem for linux 

installed and reinstalled Ubuntu 18.04 

Tried updating quartus to 20.1.1 build 720 11/11/2020

 

All i want is a simple ddr2 external memory controller so i can interface with my custom logic but it will not build 

 

does anyone have any ideas, the forums say this was fixed in 20.1 but its still here

 

 


Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br>    while executing<br>"error "An error occurred""<br>    (procedure "_error" line 8)<br>    invoked from within<br>"_error "Cannot find $seq_file""<br>    ("if" then script line 2)<br>    invoked from within<br>"if {[file exists $seq_file] == 0} {<br>		_error "Cannot find $seq_file"<br>	}"<br>    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br>    invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br>    invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br>    ("if" then script line 2)<br>    invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br>		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br>    (procedure "generate_qsys_sequencer_sw" line 943)<br>    invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."<br>    invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."<br>    ("if" else script line 2)<br>    invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br>		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br>    invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir QUARTUS_SYNTH"<br>    invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir QUARTUS_SYNTH] {<br>		set file_name [file tail $genera..."<br>    (procedure "generate_synth" line 8)<br>    invoked from within<br>"generate_synth DDR2_s0"
<html>Info: "<b>DDR2</b>" instantiated <b>altera_mem_if_ddr2_qseq</b> "<b>s0</b>"
Error: Generation stopped, 5 or more modules remaining
<html>Info: Done "<b>DDR2</b>" with 11 modules, 32 files
Info: DDR2: Generating simulation model
<html>Info: Generating <b>altera_mem_if_ddr2_emif</b> "<b>DDR2</b>" for SIM_VHDL
<html>Info: "<b>DDR2</b>" instantiated <b>altera_mem_if_ddr2_emif</b> "<b>DDR2</b>"
<html>Info: "<b>DDR2</b>" instantiated <b>altera_mem_if_ddr2_pll</b> "<b>pll0</b>"
Info: Generating DDR2_p0_altdqdqs
Info: Generating clock pair generator
<html>Info: "<b>DDR2</b>" instantiated <b>altera_mem_if_ddr2_phy_core</b> "<b>p0</b>"
<html>Info: "<b>DDR2</b>" instantiated <b>altera_mem_if_ddr2_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br>    while executing<br>"error "An error occurred""<br>    (procedure "_error" line 8)<br>    invoked from within<br>"_error "Cannot find $seq_file""<br>    ("if" then script line 2)<br>    invoked from within<br>"if {[file exists $seq_file] == 0} {<br>		_error "Cannot find $seq_file"<br>	}"<br>    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br>    invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br>    invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br>    ("if" then script line 2)<br>    invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br>		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br>    (procedure "generate_qsys_sequencer_sw" line 943)<br>    invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."<br>    invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."<br>    ("if" else script line 2)<br>    invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br>		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br>    invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir SIM_VHDL"<br>    invoked from within<br>"set seq_gen_files [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir SIM_VHDL]"<br>    ("if" else script line 2)<br>    invoked from within<br>"if {[::alt_mem_if::util::qini::cfg_is_on alt_mem_if_use_verilog_sequencer]} {<br>		set seq_gen_files [alt_mem_if::gen::uniphy_gen::generate_sequencer_fil..."<br>    (procedure "generate_vhdl_sim" line 8)<br>    invoked from within<br>"generate_vhdl_sim DDR2_s0"
<html>Info: "<b>DDR2</b>" instantiated <b>altera_mem_if_ddr2_qseq</b> "<b>s0</b>"
Error: Generation stopped, 5 or more modules remaining
<html>Info: Done "<b>DDR2</b>" with 11 modules, 11 files

 

0 Kudos
2 Replies
SyafieqS
Moderator
140 Views

HI Michael,


Can you double confirm the KDB below. I encountered this before and it work for me. Make sure you are using the correct Win 10 build for WSL and regenerate in PD

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...


SyafieqS
Moderator
118 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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