Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17049 Discussions

Problem in Qsys

Altera_Forum
Honored Contributor II
‎03-28-2014 09:56 AM
3,173 Views

Hello every body; 

I make a custom component and defined it in the Qsys tool, my custom component have an avalon mm slave bus; I faced a problem during analysing the component files in the component editor, the error is: 

 

 

*ERROR: avalon_slave_0: Slave with readdatavalid signal must support at least 1 pending read. 

 

Can any one help me; 

Thanks
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎03-28-2014 12:11 PM
2,097 Views

Read the description of the "maximumPendingReadTransactions" on page 3-6 of this document: 

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

 

It sounds like it is set to zero in your component.
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.