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Altera_Forum
Honored Contributor I
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Problem in creating a qsys custom component

Hello good evening, 

 

I have written a verilog code and i have tried to create a qsys custom component using avalon mm interface i got some problems: 

 

1. in Technology map viewer i couldn't find one of the instance of a module that included in the custom component. 

 

2. I have written a test bench in verilog which act as control signal generated by nios and i verified my verilog code with that test bench in signal tap. but when i interfaced with nios its not working, its not writing the data into the register that is pointed by the address. 

 

so i need some assitance from your side 

 

 

Thanks and regards, 

Ankur
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