Problem in the script for simulation with Active HDL

[CSoti]

I am trying to simulate a project from Quartus 18.1 Lite that also includes a system created with platform designer (avalon mm bus, triple-speed ethernet and custom ips) with Active HDL 10.5a but the script generated automatically from Quartus fails. I have installed of course the Altera precompiled simulation libraries for Active HDL (tried both pro and standard versions in case it made a difference) and I encounter the same issue.

I get the following error in Active HDL

alib vhdl_libs/fiftyfivenm_vhdl

# Adding library O.K.

amap fiftyfivenm vhdl_libs/fiftyfivenm_vhdl

# Library Manager: Library "fiftyfivenm" attached.

# AMAP: Adding mapping library O.K.

alog -v2k5 -dbg -msg 0 -work fiftyfivenm c:/intelfpga_lite/18.1/quartus/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v

# Error: VCP1010 Cannot find source file: c:/intelfpga_lite/18.1/quartus/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v

# Error: DO_001 in file stamp3_top_sim_rtl_vhdl.do line 36

I see the fiftyfivenm libraries available but the script cannot find them.

As soon as I close Active HDL I get the same error in Quartus as well.

alib vhdl_libs/fiftyfivenm_vhdl

# Adding library O.K.

amap fiftyfivenm vhdl_libs/fiftyfivenm_vhdl

# Library Manager: Library "fiftyfivenm" attached.

# AMAP: Adding mapping library O.K.

alog -v2k5 -dbg -msg 0 -work fiftyfivenm c:/intelfpga_lite/18.1/quartus/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v

# Error: VCP1010 Cannot find source file: c:/intelfpga_lite/18.1/quartus/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v

# Error: DO_001 in file stamp3_top_sim_rtl_vhdl.do line 36

Any ideas?

[CSoti]

I have also opened a case in Aldec support site and they have requested to open a case here as well in order to monitor the issue.

[KennyTan_Altera]

Hi, Check in your directory c:/intelfpga_lite/18.1/quartus/eda/sim_lib/aldec/ whether fiftyfivenm_atoms_ncrypt.v is there or not? If not, perhaps you do not download and install all the device for the Quartus prime. Thanks

[Abe]

Well, even I've run into the same issue with Active-HDL v10 . The design won't compile and even the device library compile also fails stating missing c:/intelfpga_lite/18.1/quartus/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v.

I did a little digging around and found that the tool expects the files to be in the "aldec" folder which is not there. These files are created by default in the mentor folder

c:/intelfpga_lite/18.1/quartus/eda/sim_lib/mentor and the tool expects the same files in the aldec folder.

So, I created another folder named aldec under the sim_libs directory and copied all the files from the mentor folder to this one.

c:/intelfpga_lite/18.1/quartus/eda/sim_lib/aldec/

Now when I compiled the device libraries as well as the design, the compile went through.

[CSoti]

Thanks Abe, I will try your solution and report back here. But this is just one of the problems. The generated script doesn't compile the platform_designer system libraries either.

[KennyTan_Altera]

Which Aldec simulator that you were using? active HDL or riviera pro?

There is a support tied to the OS that need to be follow on https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-tp-simulation.pdf page 4

[KennyTan_Altera]

still facing the pb?