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Problem in using 2 NIOS cores with 2 PLLs and clock sources

 

I am trying to run two NIOSII cores on an DE0-CV board. They are supposed to run two application and don't need to share any resource. I also need them to run with two different clock rates. This is my design:

***for some reason pictures are unavailable so I am attaching my project.

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module DE0_CV_SDRAM_Nios_Test( ///////// CLOCK2 ///////// input CLOCK2_50, ///////// CLOCK3 ///////// input CLOCK3_50,   ///////// CLOCK4 ///////// inout CLOCK4_50,   ///////// CLOCK ///////// input CLOCK_50,   ///////// DRAM ///////// output [12:0] DRAM_ADDR, output [1:0] DRAM_BA, output DRAM_CAS_N, output DRAM_CKE, output DRAM_CLK, output DRAM_CS_N, inout [15:0] DRAM_DQ, output DRAM_LDQM, output DRAM_RAS_N, output DRAM_UDQM, output DRAM_WE_N,   ///////// GPIO ///////// inout [35:0] GPIO_0, inout [35:0] GPIO_1,   ///////// HEX0 ///////// output [6:0] HEX0,   ///////// HEX1 ///////// output [6:0] HEX1,   ///////// HEX2 ///////// output [6:0] HEX2,   ///////// HEX3 ///////// output [6:0] HEX3,   ///////// HEX4 ///////// output [6:0] HEX4,   ///////// HEX5 ///////// output [6:0] HEX5,   ///////// KEY ///////// input [3:0] KEY,   ///////// LEDR ///////// output [9:0] LEDR,   ///////// PS2 ///////// inout PS2_CLK, inout PS2_CLK2, inout PS2_DAT, inout PS2_DAT2,   ///////// RESET ///////// input RESET_N,   ///////// SD ///////// output SD_CLK, inout SD_CMD, inout [3:0] SD_DATA,   ///////// SW ///////// input [9:0] SW,   ///////// VGA ///////// output [3:0] VGA_B, output [3:0] VGA_G, output VGA_HS, output [3:0] VGA_R, output VGA_VS );     //======================================================= // REG/WIRE declarations //======================================================= DE0_CV_QSYS u0( .clk_1_clk(CLOCK_50), // clk.clk .reset_1_reset_n(1'b1), // reset.reset_n .clk_2_clk(CLOCK2_50), // clk.clk .reset_2_reset_n(1'b0), // reset.reset_n //.key_external_connection_export(KEY), // key_external_connection.export //.key2_external_connection_export(KEY), // key_external_connection.export //SDRAM // .clk_sdram_clk(DRAM_CLK), // clk_sdram.clk // .sdram_wire_addr(DRAM_ADDR), // sdram_wire.addr // .sdram_wire_ba(DRAM_BA), // .ba // .sdram_wire_cas_n(DRAM_CAS_N), // .cas_n // .sdram_wire_cke(DRAM_CKE), // .cke // .sdram_wire_cs_n(DRAM_CS_N), // .cs_n // .sdram_wire_dq(DRAM_DQ), // .dq // .sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), // .dqm // .sdram_wire_ras_n(DRAM_RAS_N), // .ras_n // .sdram_wire_we_n(DRAM_WE_N) // .we_n );   endmodule

When I compile this, it compiles correctly and I can program my board. I use NIOSII to start a HelloWold application. I can successfully run that on core1.

 

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However when I try to run it on core2 I get an error.

 

 

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Does anybody know what I am doing wrong? I feel there is something wrong with my use of PLLs and clocks sources. But I have no clue what can be wrong. It looked working when I had both processors connected to CLOCK_50 and no PLL.

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi,

 

Yes, we can have a Multiprocessor System design without sharing the resource to run with two different clocks.

 

Can you attach the project? Is PLL shared?

 

Regards

Anand

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi,

Thank you for the reply. I attached pictures previously but it doesn't show them. I am attaching my project again. The PLL is not shared. I used a PLL for each core. I also used different clock sources and clock pins for each PLL.

P.s. I know it is possible to use one PLL with two outputs but for the purpose of my research I need to use two different PLLs.

 

Thank you,

Alireza

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi Alireza,

 

I have used your design with DE1-Nano/ Atlas kit, With some modifications(On-chip memory and integer PLL). i was able to run the design successfully.

Attached the project

 

Kindly recompile the cores, top level design and check .

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

nioscore1.JPG

 

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi,

 

I copied the qsf files to my project and successfully compiled it but when I try to compile a helloworld application it gives me error. Do you know what the problem is? should I change the memory addresses?

nios2-elf-ar -src libhal_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_ecc_fatal_entry.o obj/HAL/src/alt_ecc_fatal_exception.o obj/HAL/src/alt_env_lock.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_malloc_lock.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putcharbuf.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_gen2_irq.o obj/HAL/src/crt0.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o [BSP build complete] Info: Compiling hello_world.c to obj/default/hello_world.o nios2-elf-gcc -xc -MP -MMD -c -I../hw_bsp//HAL/inc -I../hw_bsp/ -I../hw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/default/hello_world.o hello_world.c Info: Linking hw.elf nios2-elf-g++ -T'../hw_bsp//linker.x' -msys-crt0='../hw_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../hw_bsp/ -Wl,-Map=hw.map -O0 -g -Wall -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o hw.elf obj/default/hello_world.o -lm -msys-lib=m c:/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0xf300 of hw.elf section `.rwdata' is not within region `core2_onchip_memory2' c:/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x10ec0 of hw.elf section `.bss' is not within region `core2_onchip_memory2' c:/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0xf300 of hw.elf section `.rwdata' is not within region `core2_onchip_memory2' c:/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x10ec0 of hw.elf section `.bss' is not within region `core2_onchip_memory2' collect2.exe: error: ld returned 1 exit status make: *** [hw.elf] Error 1

 

 

new1.jpg

Thanks,

Alireza

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi,

I resolved the compilation problem by increasing the size of onchip memory and base addresses. But my original problem still exists.

new2.JPG

 

The problem still exists.! I can run hello world on core1 but I face error in when I run it on core2. It looks the picture you posted also shows success on core1 but problem is core2. I am attaching my new project as well which I generated by using your qsf files.

new3.JPG

 

 

 

Regards,

Alireza

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi Alireza,

 

Check the core 2 reset signal.

i.e .reset_2_reset_n(1'b0) should be .reset_2_reset_n(1'b1),

CORE2_RESET_SIG.JPG

 

Regards

Anand

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi,

 

Thanks. Can I ask another question? Do you know if it is possible in this design to share the SDRAM ? not to share data with each other but to partition it and assign half of the SDRAM to each core.

Regards,

Alireza

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Re: Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi Alireza,

 

We are going out of the subject, Please open new case.

Which will help in keeping the community organized and easy for other user to search in community.

 

Do you know if it is possible in this design to share the SDRAM ?

Yes, shared peripheral.

 

not to share data with each other but to partition it and assign half of the SDRAM to each core.

It's similar to the Sharing Memory, which is discussed in below link.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_nios2_multiprocessor_...

 

Regards

Anand

 

 

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