Problem simulating Qsys output

[Altera_Forum]

I am working on a project with a Qsys sub-system, and am getting a fatal error when running Modelsim-ASE. My Qsys module has a PCIe core, clocks, a small on-chip RAM, some SG-DMA controllers, a clock bridge to route the pcie clock to logic outside Qsys, and an Avalon-MM pipeline bridge to route a BAR space to outside logic. 

 After generating simulation files, I run the msim_setup.tcl script, then run the "com" macro and the "elab" macro (both generated by Qsys). While elaborating, modelsim gives a vsim-3374 fata error: # ** Fatal:(vsim-3374) [path]/altera_merlin_burst_uncompressor.sv(176): MSB of part-select into 'addr_width_burstswap' is out of bounds.  Has anybody ever encountered this error?

[Altera_Forum]

Tracking back through the .sv files generated by Qsys, I found the source of the problem. If the BAR address space that the SGDMA controller sits in is smaller than 10 bits, I get the error. In my design, the only peripherals sitting on BAR2 were 4 SGDMA controllers packed tightly into 8 bits of address space. I moved the base address of one of the SGDMA controllers so that I had a 10 bit BAR address space, and the error went away. 

 The problem seems to be that Qsys was generating altera_merlin_slave_agent instances with PKT_ADDR_H - PKT_ADDR_L < PKT_BURSTWRAP_H - PKT_BURSTWRAP_L.

[Altera_Forum]

Can you file a service request with the system attached in the problematic (packed address) case so that this can be fixed.