Problem while simulating system design with DDR3 memory controller

[ASuba]

Hi

I have recently started working with Nios11 based System design using Quartus for a project. I created the system in Platform Designer (qsys) and exported it to Nios SBT for writing simple code for simulations in modelsim. In simulations i could see that Nios11 processor seems to be uninitialized and doesn't work or excecute any actions in simulations. In setting I have added onchip SRAM as reset and exception vector. I would like to do to make simple read write data from external DDR3 memory(though booting happens from On Chip ram).

[AnandRaj_S_Intel]

Hi,

Please Refer example and below link to debug.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-simulating-niosii.html

http://ebook.pldworld.com/_Semiconductors/ALTERA/one_click_niosII_docs_9_0/files/an351.pdf

DDR3 example.

https://fpgawiki.intel.com/wiki/Design_Example_-_Basic_DDR3_UniPHY_bring_up

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)