- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Good afternoon,
I'm trying to cascade two PLL's. Every PLL is fractional.
The first PLL gets Clock=75 MHz at its refclk port.
Then, I'm taking the signal from its cascade_out port and connect it to adjpllin port of second PLL.
First PLL gets RESET='0' constant,the second PLL gets RESET from inverted locked port of first PLL.
Unfortunately, nothing happens during simulation -the outputs of second and first PLL are red.
What is wrong with my cascading? Why simulation doesn't work?
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi guys,
Do you have something new about this issue?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Let me recreate the issue and will update you , in mean time kindly reset the first PLL for some period of time then try to obtain the data
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
I had my simulation in Model sim and found it is wokring
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
Kindly let me know, if you need further assistance.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page