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Problem with 2 cascaded PLL in CycloneV

AGofs
Novice
606 Views

Good afternoon,

I'm trying to cascade two PLL's. Every PLL is fractional.

The first PLL gets Clock=75 MHz at its refclk port.

Then, I'm taking the signal from its cascade_out port and connect it to adjpllin port of second PLL.

First PLL gets RESET='0' constant,the second PLL gets RESET from inverted locked port of first PLL.

Unfortunately, nothing happens during simulation -the outputs of second and first PLL are red.

What is wrong with my cascading? Why simulation doesn't work?

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4 Replies
AGofs
Novice
457 Views

Hi guys,

Do you have something new about this issue?

 

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Rahul_S_Intel1
Employee
457 Views

 

Let me recreate the issue and will update you , in mean time kindly reset the first PLL for some period of time then try to obtain the data

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Rahul_S_Intel1
Employee
457 Views

Hi ,

I had my simulation in Model sim and found it is wokring

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Rahul_S_Intel1
Employee
457 Views

Hi ,

 

 Kindly let me know, if you need further assistance.

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