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Hello, I have a problem in my simulation with the Clock Recovery during the Display Port Link Training through the AUX channel. I'm using Quartus 16.1 and the DisplayPort has the following features:
DPCD revision number: 1.2
MAX_LINK_RATE = 2.7 Gbps per lane
MAX_LANE_COUNT = 2
I use the following sequence to perform the Link Training:
// Write DPCD LINK_BW_SET to 2.7Gb/s
wr_data = {8'h0a};
aux_write (20'h00100, wr_data);
// Write DPCD LANE_COUNT_SET to dual lane with Enhanced Framing symbol
wr_data = {8'h82};
aux_write (20'h00101, wr_data);
// Write DPCD TRAINING_PATTERN_SET (Training Pattern 1 disabling scramble)
wr_data = {8'h21}; aux_write (20'h00102, wr_data);
// TRAINING_LANE0_SET
wr_data = {8'h800};
aux_write (20'h00103, wr_data);
// TRAINING_LANE1_SET
wr_data = {8'h00};
aux_write (20'h00104, wr_data);
// Read TRAINING_AUX_RD_INTERVAL
aux_read (20'h0000E, 8'h0, rd_data); => rd_data 00h = 100us
#100us => wait for TRAINING_AUX_RD_INTERVAL
// Read DPCD LANE0_1_STATUS
aux_read (20'h00202, 8'h0, rd_data); => rd_data = 00h
// Read DPCD ADJUST_REQUEST_LANE0_1
aux_read (20'h00206, 8'h0, rd_data,); => rd_data = 11h
So I update the Voltage/Pre-Emphasis with the read value.
// TRAINING_LANE0_SET
wr_data = {8'h801};
aux_write (20'h00103, wr_data);
// TRAINING_LANE1_SET
wr_data = {8'h01};
aux_write (20'h00104, wr_data);
#100us => wait for TRAINING_AUX_RD_INTERVAL
// Read DPCD LANE0_1_STATUS
aux_read (20'h00202, 8'h0, rd_data); => rd_data = 00h
// Read DPCD ADJUST_REQUEST_LANE0_1
aux_read (20'h00206, 8'h0, rd_data); => rd_data = 22h
// TRAINING_LANE0_SET
wr_data = {8'h02};
aux_write (20'h00103, wr_data);
// TRAINING_LANE1_SET
wr_data = {8'h02};
aux_write (20'h00104, wr_data);
#100us => wait for TRAINING_AUX_RD_INTERVAL
// Read DPCD LANE0_1_STATUS
aux_read (20'h00202, 8'h0, rd_data); => rd_data = 00h
// Read DPCD ADJUST_REQUEST_LANE0_1
aux_read (20'h00206, 8'h0, rd_data); => rd_data = 33h
// TRAINING_LANE0_SET
wr_data = {8'h803};
aux_write (20'h00103, wr_data);
// TRAINING_LANE1_SET
wr_data = {8'h03};
aux_write (20'h00104, wr_data);
#100us
// Read DPCD LANE0_1_STATUS
aux_read (20'h00202, 8'h0, rd_data); => rd_data = 00h
// Read DPCD ADJUST_REQUEST_LANE0_1
aux_read (20'h00206, 8'h0, rd_data); => rd_data = 33h
From now on I get always rd_data = 33h from DPCD ADJUST_REQUEST_LANE0_1 and rd_data = 00h from DPCD LANE0_1_STATUS, so the DisplayPort don't compete the Clock Recovery and I'm stuck at this point.
What could be my problem? I'm following the Link Training Clock Recovery procedure.
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