Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Problem with Gate level simulation

TRoa
New Contributor I
1,619 Views

Hi,

I made a simple design for just experimentation. In that design, I instantiated a multiplier from IP catalog(simple multiplier). Then I synthesized. Everything was ok. Then I wrote a testbench and tried to run simulation through native link.

RTL simulation is working just fine.

But when I run gate level simulation, the output of the multiplier is all XXX. Please note that when it asks about timing model, I use the same "slow model", as hinted by the prompt.

What possibly I may be doing wrong?

 

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RichardTanSY_Intel
1,570 Views

Have you followed the Gate-Level Simulation (NativeLink Flow) as per the user guide?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-tp-simulation.pdf#page=11

TRoa
New Contributor I
1,570 Views

The problem was timing. The model or the IP was not starting till 4995 ps . So What I did, I regenerated that IP with same specs, but with little less files(this time only with .v files). And problem was solved.

Now, no starting delays and IP is also working with peco seconds accuracy.

Thanks for your replay.

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