Problem with Pin assignment Cyclone V Quartus v13.1 - Critical Warning (169244):

[Altera_Forum]

Have this error occurring 

 Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank 3A have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists.  Also for 2 other banks, however there are no LVDS, RSDS or mini-LVDS inputs or outputs on the banks that bring up this error (but there are on my design on different banks)  Does anyone have a solution to this problem?

[Altera_Forum]

I am afraid, you are totally alone with your problem. Only Quartus II 13.0 SP1 is available at the moment for regular users.

[Altera_Forum]

--- Quote Start ---  I am afraid, you are totally alone with your problem. Only Quartus II 13.0 SP1 is available at the moment for regular users.  --- Quote End ---    My most humble apologizes 13.0 SP1.

[Altera_Forum]

--- Quote Start ---  Have this error occurring  Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank 3A have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists.  Also for 2 other banks, however there are no LVDS, RSDS or mini-LVDS inputs or outputs on the banks that bring up this error (but there are on my design on different banks)  Does anyone have a solution to this problem?  --- Quote End ---     See the altera quartus online help for your answer: http://quartushelp.altera.com/13.0/mergedprojects/msgs/msgs/wfiomgr_warning_too_many_se_output_share_bank_with_dedicated_lvds_output.htm This is not a Cyclone V related problem. Be careful if you create a custom FPGA pin-out: one FPGA bank has a common I/O standard. Replace some output / bidir pins with input pins coming from an other FPGA bank.  Regards,  ZS.V.

[Altera_Forum]

What's the info message under the critical warning? Did you tried I/O toggle rate assignment for the "slow" pins of your design? Be aware of this: http://www.altera.com/support/kdb/solutions/rd07082013_903.html

[Altera_Forum]

Might be worth trying but my bank is not so highly populated, also it does not line up with the error message. (The help offered does line up with the error reported but the reported error does not line up with the design entered.) Thank you.

[Altera_Forum]

Open support case at Altera's website if you feel really worried about this issue.

[Altera_Forum]

--- Quote Start ---  Open support case at Altera's website if you feel really worried about this issue.  --- Quote End ---    Message full contents Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank 3A have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists.  Info (169245): There are 16 output pin(s) with I/O standard 2.5 V and termination Series 50 Ohm  Info (169220): Location R6 (pad PAD_52): Pin fpga_d[6] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location U7 (pad PAD_53): Pin fpga_d[5] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location R5 (pad PAD_54): Pin fpga_d[8] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location U8 (pad PAD_55): Pin fpga_d[7] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location P6 (pad PAD_56): Pin fpga_d[10] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location W8 (pad PAD_57): Pin fpga_d[9] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location N6 (pad PAD_58): Pin fpga_d[12] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location W9 (pad PAD_59): Pin fpga_d[11] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location T7 (pad PAD_60): Pin fpga_d[14] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location U6 (pad PAD_61): Pin fpga_d[13] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location T8 (pad PAD_62): Pin fpga_d[4] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location V6 (pad PAD_63): Pin fpga_d[15] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location M6 (pad PAD_64): Pin fpga_d[0] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location R7 (pad PAD_65): Pin fpga_d[2] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location M7 (pad PAD_66): Pin fpga_d[1] of type bi-directional uses 2.5 V I/O standard  Info (169220): Location P7 (pad PAD_67): Pin fpga_d[3] of type bi-directional uses 2.5 V I/O standard   I will give set the toggle rate and see if it helps but my feeling is a bug in quartus.