I am building design where I need 3.0V TTL signals to connect to processor.
Problem is Quartus Pin planner does not even have option to select 3.0V LVCMOS or LVTTL. While I can do it by hand in Asigment Editor.
If Its shows up in pin planner, I just have to touch IO standard field, and it will be placed as blank.
Some One who was rewriting Quartus Prime forgot to add 2.5V and 3.0V IO standards for selection. It is incredible that this bug can be passed without correcting.
INTEL please fix it ASAP because this is major bug. I can't make my design if i can't select 3.0V IO standard. and also contact me in PM, since i was unable to find how to generate technical support ticket.
According to figure 67 and table 36, your 10CX105 only supports 3 V in I/O bank 2L, not in 3A or 3B like you show in your video. Table 33 shows that 3 V is only allowed in the 3 V I/O not the LVDS I/O.
Hello, Thank you for correct response.
Well, tats is very disappointing...
That is big problem for me. I was used to that I can connect IO bank too any voltage and get same CMOS voltage out of it. But what kind of limitation does GX part has ? This is not a problem for regular Cyclone 10 LP for same footprint and cell size.
Usually true LVDS banks are missing and 3V CMOS are abundant , but I see now that with this chip, is other way around. all FPGA's can only have 48x 3V capable pins.
Now just have to figure out how to make this work.
Thank you for support!
Since the question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.