Problem with Verilog to VHDL code porting

Altera_Forum · ‎10-25-2014

Hello all forum users.

I have Verilog code (for example).


module exclusive_or_gate_on_verilog
(
    input  SW,
    output  LEDR, LEDG
);
wire a,b,not_a,not_b,o1,o2,out_1,out_2;
// Default Qartus II logig gate for "Exclusive OR gate"
XOR  my_1_xor(  .OUT (out_1),  .IN1 (a), .IN2 (b)  );
// Combination of other gates for "Exclusive OR gate"
NOT my_1_not( .OUT (not_b), .IN (b) );
NOT my_2_not( .OUT (not_a), .IN (a) );
AND2 my_1_and2( .OUT (o1), .IN1 (a), .IN2 (not_b) );
AND2 my_2_and2( .OUT (o2), .IN1 (not_a), .IN2 (b) );
OR2 my_1_or2( .OUT (out_2),  .IN1 (o1), .IN2 (o2) );
assign a = SW;
assign b = SW;
assign LEDR = SW;
assign LEDG = out_1;
assign LEDG = out_2;
endmodule

and I can't porting this code to VHDL corretly (without Quartus II errors).


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity exclusive_or_gate_on_vhdl is
    port (
                SW    : in    std_logic_vector (1 downto 0); 
            LEDR     : out    std_logic_vector (1 downto 0); 
            LEDG : out   std_logic_vector (1 downto 0)
            );
end exclusive_or_gate_on_vhdl;
architecture BEHAVIORAL of exclusive_or_gate_on_vhdl is
signal a,b,not_a,not_b,o1,o2,out_1,out_2 : std_logic;
   component XOR
      port ( IN1 : in    std_logic; 
             IN2 : in    std_logic; 
             OUT  : out   std_logic);
   end component;
   
    component NOT
      port ( IN : in    std_logic; 
             OUT : out   std_logic);
   end component;
       
    component AND2
      port ( IN1 : in    std_logic; 
             IN2 : in    std_logic; 
             OUT : out   std_logic);
   end component;
      
   component OR2
      port ( IN1 : in    std_logic; 
             IN2 : in    std_logic; 
             OUT : out   std_logic);
   end component;
   
begin
  
    -- Default Qartus II logig gate for "Exclusive OR gate"
    
    my_xor_1 : XOR
      port map (IN1=>b,
                IN2=>a,
                OUT=>out_1);
                    
   -- Combination of other gates for "Exclusive OR gate"
    
   my_not_1 : NOT
      port map (IN=>a,
                OUT=>not_a);
   my_not_2 : NOT
      port map (IN=>b,
                OUT=>not_b);
    
    my_and2_1 : AND2
      port map (IN1=>a,
                IN2=>not_b,
                OUT=>o1);
   my_and2_2 : AND2
      port map (IN1=>not_a,
                IN2=>b,
                OUT=>o2);
   my_or2_1 : OR2
      port map (IN1=>o1,
                IN2=>o2,
                OUT=>out_2);
       
a <= SW(1);
b <= SW(0);
LEDR <= SW;
LEDG(0) <= out_1;
LEDG(1) <= out_2;
   
end BEHAVIORAL;

I specially use built-in default Quartus II logic gates (XOR, NOT, AND2, OR2). Please, don't say me about that I can use VHDL bitwise operators (y <= a or b).

Problem is that built-in default Quartus II logic gates (XOR, NOT, AND2, OR2) has name as VHDL bitwise operators (XOR = xor, NOT = not) and IN and OUT in VHDL portmaps has name as VHDL keywords (IN = in, OUT = out)

I tried rename this port names but it is not work correctly.

What must be changed in VHDL code for correctly work with built-in default Quartus II logic gates (XOR, NOT, AND2, OR2).

Thanks in advance for any help.

Altera_Forum · ‎10-25-2014

xor, not, etc are reserved words, so you cannot call your components those names. I also think and2 is an altera primative, so you probably cant use that either. You need to call in the altera primitives library.

But why the aversion to using the and, xor etc functions?

Altera_Forum · ‎10-25-2014

--- Quote Start ---

xor, not, etc are reserved words, so you cannot call your components those names. I also think and2 is an altera primative, so you probably cant use that either. You need to call in the altera primitives library.

--- Quote End ---

How I can call Altera primitives library in VHDL? Or i can't use built-in primitives in VHDL code never altogether?

--- Quote Start ---

But why the aversion to using the and, xor etc functions?

--- Quote End ---

It is not adversion - it is only educational tasks. I read VHDL specification but I can't found information about using Altera Quartus II built-in primitives in VHDL code?

---

But my VHDL code work in Xilinx ISE, because Xilins ISE has other names for built-in gates (see screenshot in attachment) and for gate-ports (I0,I1,O instead IN1,IN2,OUT).