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bit
Beginner
330 Views

Problem with terasIC DE0-CV borad (Cylone V FPGA) and different versions of the Quartus Prime Lite

Hi!

I have a problem with a terasIC DE0-CV borad (Cylone V FPGA) and different versions of the Quartus Prime Lite Edition.

I created the hack computer from the Nand To Tetris project on this board with Quartus Prime Lite Edition version 17.0.0. It was a huge project and a lot of work. In the end everything was fine and I was able to play pong and other games on this system!

When I now load the project with Quartus Prime Lite Edition version 20.1.0, I get the following error in Analysis & Synthesis:

Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete
Analysis and Synthesis.

The problem is obviously the RAM, which is too big. But that was not the case with version 17.0.0!!!

Here is the VHDL of ram16k:
---------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram16k is
port (
clk : in std_logic;
i : in std_logic_vector(15 downto 0);
load : in std_logic;
address : in std_logic_vector(13 downto 0);
o : out std_logic_vector(15 downto 0)
);
end ram16k;
architecture behavior of ram16k is
type ram_t is array(0 to 16383) of std_logic_vector(15 downto 0);
signal ram_s : ram_t := (others =>(others => '0'));
begin
o <= ram_s(to_integer(unsigned(address)));
process (clk)
begin
if (falling_edge(clk) and load = '1') then
ram_s(to_integer(unsigned(address))) <= i;
end if;
end process;
end behavior;
-----------------------------

All Analyses & Synthesis settings are on default. "max_number_of_registers_from_uninferred_rams" is set to -1 (unlimited)!

I am not an FPGA/VHDL expert, I have only build this computer system and have learned during this work a lot about FPGA and VHDL but obviously not enogh to find an explanation for this error. Has anyone an idea what the reason could be?

If anyone is interested to get all VHDLs of this project, please contact me, I provide them under Creative Commons CC BY 4.0

Thank's a lot for help!

0 Kudos
10 Replies
294 Views

Hi,


Can you share the compilation report for both software version?


Thanks.

Best regards,

KhaiY


bit
Beginner
286 Views

Here are the two compilation reports zipped in text and html format.
Best regards
Helmut

274 Views

Hi Helmut,


The error message in the compilation report is different from the error you shared in this post.

In the compilation report:

Can't read Quartus Prime message file C:/Users/bit/Desktop/Hack Computer/db/Flow Messages are not contained in a QMSG file..


> The software cannot read the content in C:/Users/bit/Desktop/Hack Computer/db/Flow Messages. Kindly check if this file exists and you have the permission to read and write the file


In this forum post:

Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis.


>CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified one or more sets of registers that act as RAM. However, when creating nodes as RAM, Analysis & Synthesis cannot convert all the sets of registers into RAM megafunctions to implement the register logic with M-LAB memory blocks, M4K memory blocks, M9K memory blocks, M-RAM memory blocks, or M144K memory_blocks. As a result, a large number of registers remain in the design, which can cause longer compilation time or result in insufficient memory to complete analysis and synthesis.


ACTION: To avoid problems when processing the design, use coding styles that allow Analysis & Synthesis to infer RAM. Refer to "Recommended HDL Coding Styles," in the Quartus Prime Handbook for examples of coding styles. If the current design already matches one of the suggested coding styles, make sure you turned on the Auto RAM Replacement logic option. You can also replace the logic in the Verilog Design File or VHDL Design File with an explicit instantiation of a RAM megafunction. Otherwise, no action is required.


CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified one or more sets of registers that act as RAM. However, Analysis & Synthesis cannot convert the sets of registers into RAM megafunctions because the target device of the current design does not have dedicated RAM hardware. As a result, the registers remain in the design, which can cause longer compilation time or result in insufficient memory to complete Analysis & Synthesis.


ACTION: To avoid problems when processing the design, change the target device to one that has dedicated RAM hardware, or remove the sets of registers that act as RAM from the design. Otherwise, you can set the value of the assignment max_number_of_registers_from_uninferred_rams to a larger value or infinity (-1).


Thanks.

Best regards,

KhaiY



bit
Beginner
269 Views

Hi KhaiY!

Thank you for your detailed answer! But I think this error in the "Flow Messages" section is not so important, because it occurs in both compilation processes. I have not such a file in this directory.

To put it more clearly:
(1) 17.0 Compilation (with Intel Quartus Prime 17.0) is successful and leads to a running Nand to Tetris Hack computer system with a pong game.

(2) 20.1 Compilation (with Intel Quartus Prime 20.1) stops with the error message of this thread, you can find it in the "Analysis & Synthesis" section under "Analysis & Synthesis Messages". At this point the compilation stops.

With both versions, I used the same VHDL files and the same IP-RAM for the VGA-memory.

Thank you very much
and best regards,
Helmut

259 Views

Hi Helmut,


Could you share the design for investigation?


Thanks.

Best regards,

KhaiY


bit
Beginner
255 Views

Hi KhaiY,

 

here are all design files and a short usage description:

  • Unzip the archive "Hack Computer.zip"
  • Start Quartus Prime Lite Edition (17.0)
  • Create the project with the "New Project Wizard"
    1. Select as working directory the created folder “Hack Computer”
    2. Use as project and top-level entity name "computer"
    3. Select as project type "Empty project"
    4. Add All Files form the working directory
    5. Select as Device "5CEBA4F23C7"
    6. Finish the "New Project Wizard"

  • Import the default DE0-CV assignments:
    Assignments, Import Assigments: DE0CV_default_assignments.qsf
    (from project directory)

  • Compile

  • Program the board (you need a vga monitor and a qwertz-ps2-keyboard)

  • Play pong

Best regards,
Helmut

233 Views

Hi,


There is no Quartus project/settings file in the ZIP attached. Kindly provide the design.qar file by clicking on Project > Archive Project > Archive.


Thanks

Best regards,

KhaiY


bit
Beginner
226 Views

Well, here is a zip file, which contains the whole Quartus Prime project, created with Version 17.0. With this Quartus Prime version the project can be compiled and transfered to the Terasic DE0CV board. With a PS2-keyboard and an VGA monitor connected to the board, the implemented pong game can be played well.

Using the same files with Quartus Prime 20.1 the compilation fails.

Best regards
Helmut

209 Views

Hi Helmut,

 

RAMs can only be inferred if the read logic is synchronous in the software. I modified the ram16k.vhd and it passed the compilation.

 

Thanks.

Best regards,

KhaiY

 

200 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

Khai Chein


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