Hello, I'm trying to implement the Sobel algorithm as a Nios2 custom instruction. I write one frame in one external DDR ram and after I change the color mode to gray scale. The trouble starts when I try to apply the Sobel algorithm. The first thing that I do is write 4 pixel lines in a internal ram that I use as cache. Then I read the necessary pixels to apply the Sobel algorithm, the problem is that the value is all times 0. This is my final degree project and I'm really stuck then I'd be really grateful if someone can help me.
Or use signaltap to look at what is actually happenning.It might be worth doing some very simple actions - just to prove anything is happening at all.
Thanks for the advices. I was trying to use the modelsim but I dont know if there any way to simulate the ram port. I will be really grateful if someone can help me more specific because I'm really lost with this. I'm dont know how to use the signaltap software and the problem is that I don't have to much time to learn because the deadline is so close.
Basically you have 2 designs to simulate: the files, you have written for Sobel algorithm and your QSYS system. Does your Sobel work at all? Can you describe better your system? Do you use any hardware or it is just simulator-thesis? You will not go far without Signal Tap if you need to show somebody your project on hardware.
Hello, I'm trying to implement it on the Nios II Embedded Evaluation Kit. I'm taking a frame from a video stream and storing it in RAM. After that I'm converting this frame to gray scale and again saving the result in RAM.To write the frame in RAM, I'm storing the pixel stream in one FIFO and when it reaches a level I'm making a burst write. When the frame is in memory, I'm reading the pixels from the memory to one FIFO, I'm taking one pixel from it, I'm converting it to gray scale and I'm storing it to another FIFO. When the second FIFO reaches a level I'm making a burst write to RAM. This works almost fine and after this I'm avaiable to read with the Altera IP "FrameReader" one grayscale frame and show it in the LCD of my Nios II Embedded Evaluation Kit. The next step will be execute the sobel algorithm. This algorithm detects the objects borders in one frame. In order to do that the algorithm takes the pixels around one pixels and makes a couple of operations with they, this operations are made in the stages 2 to 4. In the stage 5 the result will be write in one FIFO and again when this FIFO reaches one level I'll make a burst write. This works fine, I guess, however the stage 1 is not working. Before the stage 1 starts I read the pixels from RAM and stores it to one FIFO (this should work because is the same as the gray scale converter) then I get one pixels from it and stores to Sobel_ram_instance. Sobel_ram_instance is a altsyncram. In the Sobel_ram_instance I store 4 lines of pixels, Each line contains 800 pixels in gray scale. When I have stored 3 lines I start the stage 1, in this stage I get the pixels arround the selected pixel and store they on the the array g but this array all times have 0s. Currently I'm using watchdogs to test what happen but maybe I should learn about sigtap, do I need add something special to my project in order to use it?.
You can find Signal Tap in Quartus II under Tools menu. Then you add the clock for acquisition, the interesting signals, set how much samples you want to see and re-compile the design. The procedure is well described in Quartus II handbook and it is not complicated. You can see with Signal Tap what is really happening in your FIFOs and debug it easily.
Thank you so much the Signal Tap was really useful and really easy to include in my project, it's help me so much.