Pull Down

[Altera_Forum]

Hi, 

someone knows a way to force with quartus the FPGA outputs with a pull down? It's very important for me to have some pin set to 0 at the start, but without forcing them externaly.... Thanks

[Altera_Forum]

I guess that you need to add some vhdl code to drive them '0' and "drive" them 

to Z after a certain amount of time (counter).

[Altera_Forum]

hi, 

the problems that I have, it is on a input pin of a jtag cable, not on a output. I explained bad excuse me!

[Altera_Forum]

You will need to add a pull down resistor to the board or perhaps make a JTAG cable adapter so your cable plugs into it, then it plugs into the board.

[Altera_Forum]

Then is there no possibility to do it with FPGA? Am i obliged to make it externally?

[Altera_Forum]

How about using the "power-up level" assignment for that pin, maybe that could help

[Altera_Forum]

What's driving the pin and why do you need it pulled-down? I'm assuming whatever is supposed to be the driver isn't actually driving for some reason. Is it the FPGA that needs to be driven low when it goes into user mode? What about using the weak pull-up and then inverting the input?  

 If you can't invert the input(because you'd be changing the functionality once the external driver is active), use the weak pull-up on the pin. If the pin drives a register, make sure that it powers up to 0(which will happen automatically). Have another register which is the clock enable for this register. This CE register will also power up to 0, and its D input will be driven by VCC. It will be clocked by a falling edge on the input pin. So until your external driver becomes active and drives a negative clock edge, the input register will have its clock enable turned off and will be ignoring the external input.  (There's also a solution if there is no input register, but it involves a mux and will probably have a glitch)  Will it work? Most likely.  Is it hokey? Absolutely.  Be sure to disable Power-Up Don't Care, so the clock enable register doesn't get synthesized to power up to 1 and get synthesized out.  (Note that I don't know what you're situation is, and there's probably a better solution if you provide more details. What's the external driver? Why isn't it driving? Why does the input need to be pulled down when it comes out of reset? Is the input a clock or data signal? Anything else that you think might be relevant.)

[Altera_Forum]

I'm testing an ASIC on the FPGA.The fact is that, if this pin start at 1, all the device will entry in debug mode. I want absolutly it a 0. I'm testing the functionality and I haven't a board driving all inputs at the moment. For this reason I will desire to be able to decide their condition on FPGA, but there is only the possibility of a weak pull up and not of a pull down. I hope there is some tricks to do it! At the moment there's no register on this data input pin.

[Altera_Forum]

Since you have the source, and since nothing is driving the pin, use the pull-up and put an inversion on the input. You get the same affect. Once you get a board driving it(and I assume it will drive it low) then you can remove the inversion in your design.

[Altera_Forum]

In reality this pin is linked by a wire to a jtag cable that leave it in a tristate mode when it didn't use it... then I can't invert it...