My name is Ganapathi Francis Joseph , I have a couple of questions on Altera FPGA PCIExpress IP cores and Development SDK.
1. I did find from your web-site for Intel Intellectual property for PCI Express 3.0 Gen - in the link
PCI Express (PCIe) Core
from Northwest Logic
for devices : Cyclone® V SoC, Arria® V SoC, Cyclone® IV, Stratix® V, Intel® Arria® 10 SoC, Stratix® IV, Intel® Stratix® 10, Cyclone® V, Arria® V, Intel® Arria® 10
Q: How do I license this IP from Intel or Northwest ?
Q: If I do have to license from Intel - what is the cost of this IP for PCI Express 3.0 Gen ? Also do you provide full source code ?
2. There are open-source IP from Intel for PCIe Gen 1.0 and 2.0 which exist in Qsys development tool as I garner from this link
documentation for this : https://fpgawiki.intel.com/wiki/PCI_Express_in_Qsys_Example_Designs
Q: Can I integrate this open source IP into the development environment of Intel for Altera FPGA ?
Q: The PCIe1.0 and 2.0 exists in Qsys , If I use Quartus Prime 17.0 ca I compile and use as such your open-source IP ( IP compiler user guide says , https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/ug/ug_pci_express.pdf , I can compile Qsys in Quartus development environment ?
3. Intel Altera Cyclone V development environment , .
Q: Quartus development environmentr SDK , I garner there are two versions
one free version and one verions to be licensed , what is the license cost of quartus SDK and
what Intellectual properties comes along with this license ?
Q: If I use the free version of quartus development SDK does it contain all free IP tfrom Intel ?
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