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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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QSYS 1st timer -- JTAG to Avalon Master Bridge fails in System Console

Altera_Forum
Honored Contributor II
‎05-03-2016 11:21 PM
1,521 Views

Newer user of QSYS and System console here. 

 

I have a JTAG-Avalon master connected as in qsys interconnect picture below. When I try to open service to the only master that is recognized (named phy_0) it fails. 

 

1. Why is the master called phy_0? (I thought it should be master_0 - is this another IP block? 

2. Why does to open service fail? 

 

(See second picture of the system-console for commands and hierarchy of what system console is able to "register") 

 

IDEAS? THanks! 

Forest 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12180&stc=1  

http://www.alteraforum.com/forum/attachment.php?attachmentid=12181&stc=1
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Altera_Forum
Honored Contributor II
‎05-04-2016 06:36 PM
599 Views

Could you post your images in a zip file or use a different format? The forum has reduced their size and they are unreadable.

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Altera_Forum
Honored Contributor II
‎05-04-2016 07:22 PM
599 Views

Oh yeah, thanks for pointing that out. clips.zip attached.

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