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QSYS ERROR

Hi

I'm trying to generate a system including HPS(Hard Processor System) of the Cyclone V SoC in Quartus Web Edition Qsys. At the "Generate HDL" stage I got the following errors:

Warning: system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Error: domain_0_default_slave: altera_error_response_slave does not support generation for VHDL Simulation. Generation is available for: Quartus Synthesis, Verilog Simulation. Error: Generation stopped, 175 or more modules remaining Error: ip-generate failed with exit code 1: 2 Errors, 8 Warnings Warning: system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Warning: system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Error: Third-party timing and resource estimation model project creation failed: C:/altera/15.0/quartus\bin64/quartus_sh -t quartus_greybox.tcl

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