Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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QUARTUS PRIME LITE 22.1 WAVEFORM SIMULATION NOT WORKING

pharez
Beginner
925 Views

I just recently installed Quartus and I have been trying to simulate for days simple and gates using vhdl and block diagram/ schematics it compiles with non error I cant run simulation from tools either. im a beginner but I can't find anything to help me remotely I have worked with simulation platforms and electronics but this is just too annoying. I have fixed every error and there's no error that is given to me. it simulates but the output doesn't change and the forced unknown keeps on showing up. took days to get here yet its still NOT WORKING!!!!!!!!

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8 Replies
sstrell
Honored Contributor III
907 Views

Without showing the design or more details on what you've tried and what your expected results are, it's hard to help.  Provide more info if you can.

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pharez
Beginner
816 Views

The design i tried was a simple AND gate using VHDL i set the simulator all the options setting but when i create a new wafeform simulation and get all the nodes in and try to simulate, the output continues to remain XXXXX 

 

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SyafieqS
Employee
899 Views

May I know if there is any update from previous reply?

More information needed here.


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SyafieqS
Employee
841 Views

Let me know any update from previous reply


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pharez
Beginner
816 Views

The design i tried was a simple AND gate using VHDL, i also tried using the block diagram and other gates, i set the simulator all the options and setting but when i create a new waveform simulation and get all the nodes in and try to simulate, the output continues to remain XXXXX and it doesn't report any errors

 

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SyafieqS
Employee
776 Views

Are you using Wavefom university?

Assuming yes, Any message when running functional simulation?

In wvf, can easily create tb, assign count value to the signal, run simulation will auto generated the tb, by right should be working.

Also, please show snippet of your code, will be better.


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RichardTanSY_Intel
699 Views

Hi @pharez 

 

I wanted to suggest trying out the "counter" design template available in Quartus.

 

You can simply right-click on a blank Verilog/VHDL file and select the counter template. This can help eliminate any potential design or schematic issues causing the problem. In any text editor, right-click->Insert Template -> Verilog HDL -> Full Designs -> Arithmetic -> Counters

 

Additionally, I recommend not spending too much time learning waveform simulation. As your design becomes more complex, it's recommended to use the Questa Intel FPGA Edition simulation tool.

It can handle more intricate designs and provide better insights.

Link: [https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html]

 

Hope these tips help! Let me know if you have any further questions or need additional assistance.

 

Best Regards,

Richard Tan

 

 

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SyafieqS
Employee
652 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey


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