Unfortunately, qsim is not supported and has been replaced with Simulation Waveform Editor (Go to File>New>University Program VWF).
I recommend that you download and use ModelSim-Intel FPGA Starter Edition for simulation.
p.s. Don’t forget to Reply, and Select the Best Solution. :)
Thank you for your reply. I want to perform the synthesis of a digital circuit to calculate its area/delay/power. I have downloaded a pdf regarding Qsim and I have got an impression that it can calculate the processing time required by a digital circuit. I do not know if Simulation Waveform Editor or Modelsim can calculate the processing time of a circuit.
For example: I have a 2x1 mux and I need to calculate the time taken by mux to provide output once I change the input. I know that I can calculate the processing time using Synopsis/Cadence software, but I was wondering if Altera Quartus software can also do the same?
I want to perform the synthesis of a digital circuit to calculate its area/delay/power.
> You can do that with power analyzer tool though I am not expert in that tool.
I do not know if Simulation Waveform Editor or Modelsim can calculate the processing time of a circuit.
> You can perform timing simulation with Simulation waveform editor, in which the logical functionality of the design is tested in the presence of delays in order to observe the actual propagation delays in our circuit.
It means that the power consumption can be calculated using power analyzer tool, but that is available in the standard version of quartus prime as given in the link you shared, not in the quartus prime light version.
Also, processing time calculation of a digital circuit is not possible in quartus prime lite software.
This is my understanding. Please let me know if you could suggest me any method to calculate the processing time using an open source software. Thank you for your time.
Power analyzer tool should be available in lite version. You can refer to the manual below to check the feature supported in lite.
I take back my word on timing simulation, it only support Cyclone IV and Stratix IV device. Instead:
(1) You can use Signal Tap Logic Analyzer to capture the signal triggered.
(2) Depending on the constrain set for that path of the mux, you can use timing analyzer if the timing able to close that path of the mux.
I am actually trying to synthesize asynchronous circuit without a global clock, therefore I won't decide the constraint before. I think it is not possible to calculate the processing time of a self-timed circuit using Altera. Thank you for your replies.