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I'm generating RTL with the Platform Designer for a DE1-SoC board. I use an Cyclone V HPS IP and an altera_avalon_new_sdram_controller IP. When generating RTL, I received the following error:
Error: border: Error during execution of script generate_hps_sdram.tcl: p0: add_fileset_file: No such file /tmp/alt8264_8661485573042951939.dir/0003_p0_gen/hps_sdram_p0_altdqdqs.v
I'm not sure why this is happening. This directory also points to my /tmp, which doesn't belong to quartus / qsys.
I have attached my system setup below:
*System details*
OS:
Distributor ID: Ubuntu
Description: Ubuntu 18.04.3 LTS
Release: 18.04
Codename: bionic
Computer:
Intel NUC NUC8I7HVK Mini PC, Intel QuadCore i7-8809G
*Graphics card details*
Advanced Micro Devices, Inc. [AMD/ATI] Polaris 22 [Radeon RX Vega M GH]
(rev c0)
*Quartus edition(Lite/Pro/Std)*
Quartus Lite 19.1 Lite
The full log is attached bellow:
Error: border: Error during execution of script generate_hps_sdram.tcl: p0: add_fileset_file: No such file /tmp/alt8264_8661485573042951939.dir/0003_p0_gen/hps_sdram_p0_altdqdqs.v
Error: border: Error during execution of script generate_hps_sdram.tcl: Generation stopped, 4 or more modules remaining
Error: border: Execution of script generate_hps_sdram.tcl failed
Error: border: Picked up _JAVA_OPTIONS: -Xmx32g -Xss8912k -Xms16g
Error: border: 2020.01.03.15:59:51 Info:
Error: border: ********************************************************************************************************************
Error: border:
Error: border: Use qsys-generate for a simpler command-line interface for generating IP.
Error: border:
Error: border: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.
Error: border:
Error: border: ********************************************************************************************************************
Error: border: 2020.01.03.15:59:53 Warning: Ignored parameter assignment device=5CSEMA5F31C6
Error: border: 2020.01.03.15:59:53 Warning: Ignored parameter assignment extended_family_support=true
Error: border: 2020.01.03.15:59:57 Warning: hps_sdram: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Error: border: 2020.01.03.15:59:57 Warning: hps_sdram.seq: This module has no ports or interfaces
Error: border: 2020.01.03.15:59:57 Warning: hps_sdram.p0: p0.scc must be exported, or connected to a matching conduit.
Error: border: 2020.01.03.15:59:57 Warning: hps_sdram.as: as.afi_init_cal_req must be exported, or connected to a matching conduit.
Error: border: 2020.01.03.15:59:57 Warning: hps_sdram.as: as.tracking must be exported, or connected to a matching conduit.
Error: border: 2020.01.03.15:59:57 Warning: hps_sdram.c0: c0.status must be exported, or connected to a matching conduit.
Error: border: 2020.01.03.15:59:57 Warning: hps_sdram.p0: p0.avl must be connected to an Avalon-MM master
Error: border: 2020.01.03.15:59:57 Info: hps_sdram: Generating altera_mem_if_hps_emif "hps_sdram" for QUARTUS_SYNTH
Error: border: 2020.01.03.15:59:58 Info: pll: "hps_sdram" instantiated altera_mem_if_hps_pll "pll"
Error: border: 2020.01.03.15:59:58 Info: p0: Generating clock pair generator
Error: border: 2020.01.03.15:59:59 Info: p0: Generating hps_sdram_p0_altdqdqs
Error: border: 2020.01.03.15:59:59 Error: p0: add_fileset_file: No such file /tmp/alt8264_8661485573042951939.dir/0003_p0_gen/hps_sdram_p0_altdqdqs.v
Error: border: while executing
Error: border: "add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $generated_file"
Error: border: ("foreach" body line 4)
Error: border: invoked from within
Error: border: "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_altdq_dqs2 "${name}_" "DDR3" $tmpdir QUARTUS_SYNTH] {
Error: border: set file_name [file tail $genera..."
Error: border: (procedure "generate_synth" line 13)
Error: border: invoked from within
Error: border: "generate_synth hps_sdram_p0"
Error: border: 2020.01.03.15:59:59 Info: p0: "hps_sdram" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: border: 2020.01.03.15:59:59 Error: Generation stopped, 4 or more modules remaining
Error: border: 2020.01.03.15:59:59 Info: hps_sdram: Done "hps_sdram" with 7 modules, 13 files
Info: border: "hps_io" instantiated altera_interface_generator "border"
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Hi,
You were seeing the error because
You does not have "make" installed and causes the mentioned script to fail as there are no return checks within the dynamically generated .tcl script.
We are in the process of making an enhancement to have a clearer error message.
Thanks,
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Hi KTan_Intel,
I actually have the make command installed, and build-essential as well. However, the same issue keeps on popping up.
Another experiment I did was to create a clean project and re-import the .qsys file, and then generate RTL. This time the same error didn't show up; but if I were to slightly modify the qsys project and regenerate the RTL code, the same "border" error would show up from time to time. Do you happen to know what the cause could be? For now, I can do a temporary fix that cleans up the project before generating RTL every time.
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Can you attached your design.qar here? I will try on my side and see how it goes.
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Any update?
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Hi KTan_Intel,
Thanks for checking in; please find the .qar file in the attachement.
Thanks!
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I try the generation from my side and I did not get any error. For your quartus, did you install all the device? Can you try it on different machine instead?
Can you double check this kdb? https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2018/error--border--error-during-execution-of-script-generatehpssdram.html
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any update?
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Hi KTan_Intel, I tried it on ubuntu 16.04 and it worked. Hence I'm closing this issue ticket for now. Thanks for helping!

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