Qsys SPI(3 Wire Serial) control

[Altera_Forum]

Hey, I am trying to build a SPI interface using the Qsys tool for a Cyclone IV I am using but I can't seem to figure out how to use the SPI (3 Wire Serial) IP in the catalog. It requires an Avalon MM control port input and when I provide it the output from the Merlin_Slave_Agent I cant figure out how to set the data output from the dozen or so inputs. A similar issue arises when I I try to make the Cyclone the SPI slave. Is there a document somewhere that outlines the spi_control_port inputs and how to send it data? 

 My ultimate goal is to have a SPI master that will send and read data any time a new data to send value is entered (or maybe a send bit is toggled). the data read from the slave would then be displayed on LEDs. Similarly, I want to have a SPI slave that will read and send data any time it's chip select is selected. the read data will then be displayed on a set of LEDs.  Thanks

[Altera_Forum]

Have a thorough read through the datasheet for the 'spi core' (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/n2cpu_nii51011.pdf). This covers all aspects of the peripheral, what it should connect to, and how to control it. 

 You can also refer to the spi slave to avalon master bridge design example (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html) on Altera's website. This does everything you require.  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  Have a thorough read through the datasheet for the 'spi core' (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/n2cpu_nii51011.pdf). This covers all aspects of the peripheral, what it should connect to, and how to control it.  You can also refer to the spi slave to avalon master bridge design example (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html) on Altera's website. This does everything you require.  Cheers, Alex  --- Quote End ---    Alex,  I looked at the SPI slave to avalon master bridge design example, it looks like in Quartus 16.0 this example is demo for internal loopback? If I want to use it as SPI master, I guess I have to link each pin using pin/chip planner to external interface?  Benson

[Altera_Forum]

I've not installed Quartus 16. However, I'd be amazed if they've changed any part of the SPI core when moving to it.  

 If using the core as a master - to connect to slaves external to the FPGA - then yes. You are going to need to export the SPI signals (SCLK, SS_N, MISO & MOSI) and assign them to pins in the pin planner.  Chapter 9 of the "embedded peripherals ip user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf)" covers the core, and how to configure it, in detail.  Cheers, Alex