Qsys: pll/clock warnings

[Altera_Forum]

Hi, 

 This is the first post from me here, so I hope I've posted in an appropriate forum section. Anyhow, I am having problems with using Qsys. I am using Quartus II Web edition 15.0  I am using Cyclone IV to try and communicate to FTDI USB transciever via SPI at ~20MHz. Other internal logic will be operating at 375MHz and there will be a 125MHz clock to external DDR SDRAM. So I decided to create/connect these modules in Qsys for ease of use but the following warnings popped up: http://s21.postimg.org/fe646h14n/warnings.png (http://postimage.org/)   And this is how I got everythign wired up in Qsys: http://s21.postimg.org/mvfbloqnr/connections.png (http://postimage.org/)  I've used Avalon ALTPLL for pll as it was the only avaliable for me. What is the problem, how can I fix it?  Thanks!

[Altera_Forum]

Hi, 

 I believe you have some screenshots or attachment in your post which is not showing up in the thread.

[Altera_Forum]

The warnings are pretty explanatory. Lets start with the bottom two. 

 You have two interfaces 'ddr_sdram_control' and 'spi_control', both of which are exported from Qsys (for external connection), but the clock which is used for both of those interfaces is not available externally. So how are you going to clock data in/out of the interfaces if you don't have the clock available. You should add a pair of "clock sources", one for each of the c0 and c1 counters - these are the clocks which are clocking your memory and spi controller, so you will need these to run any logic interfacing with the memory and spi. For the clock sources, connect the reset up to the controllers as well (you can have more than one reset connected to a given controller). This way you can feed the locked signal back in to the system - to reset the controllers when the PLL is not yet locked.  The spi controller has an IRQ pin - interrupt request. If you are not using it, then ignore the warning, it is just saying that it is not connected. The simplest way to get rid of the warning is to export it like you have the other interfaces - there is nothing to say you can't leave it unconnected outside Qsys.   The PLL has a control interface 'pll_slave' for dynamic reconfiguration. This is not exported either. Again if you don't need it you can ignore the warning, or you can export it.

[Altera_Forum]

Thanks for explaining. Worked like a charm!