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Qsys testbench(verilog) generation error!!

Altera_Forum
Honored Contributor II
999 Views

Hi,  

I am trying to generate a Qsys testbech for a custom IP having avalon-ST sink, avalon-ST source and avalon-MM write slave interfaces. I have exported all the interfaces of IP but when I generate the testbech, following error appears: 

 

"TB_Gen: Design has 5 but instance has 0 exported interface 

Error: Design has 5 but instance has 0 exported interface..." 

 

does anybody have any suggestions or solution to the problem?? 

 

From the Generation tab in Qsys, i have selected following options for simulation: 

 

Create simulation option: None 

Create testbench Qsys model: Standard, BFMs for standard Avalon interfaces 

Create testbench simulation model: Verilog 

 

regards, 

ihtesham
0 Kudos
1 Reply
AAjit2
New Contributor I
216 Views

I came upon this error when I got the same one with mine and I was sorry to see that this had received no responses. Presently it's Platform Designer (no longer Qsys) and the conduit error only happened for me when it couldn't detect the custom IP file in the directory or if the naming of the .qsys file clashes with an existing one. I changed the name of the .qsys file and moved it to the right directory and was able to generate a testbench with no errors. This is what worked for me. 

This may not be much use to you after all this time, but for anyone else who stumbles onto here with the same problem can try what I did. 

Cheers!

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