Quartus 12.0 Missing Bus Signal

[davidr1529]

Hello, I've been trying to debug a large circuit for a while, and with no luck I decided to try to replicate some errors in smaller circuits.  I've been having no issue with the general compilation, errors only come in when trying to use Create/Export to a .hdl.  In particular, I think my problem is with buses.  What is wrong with my first circuit?  The second circuit is part of the bigger one that I've been having problems with, I've tried everything (renaming pins on my subcircuits, I have this weird one_to_two subcircuit, weird names with insts to resolve errors), I'm getting nowhere.  At first, I wanted to connect the Y pins directly to the B[3..0] bus input for "alu-first", which also happens to be outputted as a bus through "SOMEBITS[3..0]".  I thought I could just connect the buses together but that didn't work, then tried it individually and am still getting weird errors as shown.

Anything you can do to help would be appreciated.  I'm a beginner doing this for my digital logic assignment, so please be patient.   Sorry for the wallpost.

[sstrell]

For both of these, you don't have a name on the busses before splitting them off to individual signals.  You need GROUNDS[3..0] in the first and B[3..0] in the second.  Busses don't pick up names from logic they're connected to in a schematic.  You have to give them a name which can then be bit sliced.

Better suggestion: learn an HDL and get away from schematics if you can.

[Nurina]

Hi,

Does the above comment help?

Regards,

Nurina