Quartus 12_Analysis and Synthesis Failed_Help

[Altera_Forum]

Hello,I am trying to create a simple RAM in my FPGA memory, and allow a microprocessor to read from the memory. I am attaching my code for the reference.I am getting the following error while compilingError (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis.Please advice.Thanks,Manoj

[Altera_Forum]

Your code requires memory access in two separate processes, one for write and one for read. 

This possibly implies the compiler can't infer a simple synchronous ram, and it could implement far more logic than what is actually required. Probably it implements a dual port ram or it infers latched to cover all data paths. Please follow the guidelines in this document for inferring ram functions: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf (read from page 14)

[Altera_Forum]

I agree with Cris72. After I read and understood the chapters "Recommended Design Practices" and "Recommended HDL Coding Styles" of the Quartus II handbook (volume 1) I was able to avoid considerable waste of FPGA resources. I'm gradually able to predict what hardware will be generated by various statements and found that helps a lot.

[Altera_Forum]

Thank you Cris and Galfonz, It worked for me!