Hi,I'm designing a fairly complex system mostly based on Avalon MM architecure. I want to simulate my slave components with the Avalon BFMs. Succesfully worked through the examples in the document "Introduction to Avalon Verification IP Suite". Additionally, I watched this demonstration video: http://www.altera.com/education/demonstrations/qsys/simulation/simulation-online-demo.html (http://www.altera.com/education/demonstrations/qsys/simulation/simulation-online-demo.html) There is still alot I have to understand, but I felt ready to simulate my first own QSys component with Avalon BFMs. The component already runs synthesized on a Cyclone V and I also have done Modelsim simulations with it where I wrote the Avalon MM master side in my own VHDL testbench. Since I felt that this is not a good verification, I now want to use the BFMs. So I started QSys and selected the component that I want to verify from the Library. The component is written in VHDL and contains 1 file with the entity and architecture definition and 1 library file where I have put some system wide constants. As I said, that component (along withe the library) works fine in a system that I already have synthesized. I exported all signals of that component like I learned in the above mentioned tutorials. I go to the "Generate/Generate Testbench System . . ." menu entry of Qsys and select "Standard, BFMs for standard Qsys interfaces" and the simulation model should be created in VHDL (since my component is in VHDL and I think Modelsim Altere (free edition) does not support mixed-language simulation). Okay, when I hit generate, it finally comes up with this error: Error: ads1158_interface_0: ads1158_interface does not support generation for VHDL Simulation. Generation is available for: Quartus Synthesis. Error: Generation stopped, 2 or more modules remaining Info: ads1158_bfm_test_tb: Done "ads1158_bfm_test_tb" with 12 modules, 35 files Error: ip-generate failed with exit code 1: 2 Errors, 0 Warnings Error: There were errors creating the testbench system. Can somebody please explain what this error message means and how I can get over that? Thanks, Maik
Sorry for asking, I just solved it myself: You have, in the component editor under the Files tab, to add the same files in the aera "VHDL Simulation Files" like you put them in "Synthesis Files".So this one is solved, but prepare for the next question in a new thread ;-) ! Regards, Maik
Hi, I am having the same issue. I am trying to open the component editor, but I can't seem to find a way to open it for an existing component. Every manual I read just shows how to open it for new components. I am using quartus prime version 20.2.0 Pro edition. If you can help me out with this, I'd greatly appreciate it.
I am trying to simulate the top level of a design. To do so, I was trying to run the "ip-setup-simulation" utility. When I ran it, I got about 430 errors where SPD files were not found. To fix that, I ran qsys-generate on each qsys system in the design for simulation, and after doing that, I reduced the errors to 16 SPD files not found. When looking at the output of the qsys-generate for those specific ip cores, I noticed the same error message as in this threat: "..does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis". I've seen a couple of threats with similar errors stating that this can be fixed specifying simulation files in the "files" tab in the component editor as shown in this threat, so I was trying to do the same to fix my issue. Any help would be appreciated.
What IP are you trying to simulate? They may not support Platform Designer testbench simulation and may require a different method to simulate.