I try to simulate a design with a LPM_MULT IP-Core in square mode. I'm able to compile the design but the simulator fails with the following error message:
Error: (vsim-3389) mul_sqr.v(53): Port 'sclr' not found in the connected module (6th connection).
The relevant content of the verilog file looks like this:
altsquare altsquare_component ( .aclr (aclr), .clock (clock), .data (dataa), .result (sub_wire0), .ena (1'b1), .sclr (1'b0));
If i remove the "sclr"-Line the simulation works. It looks like the IP-Core is not properly generated.
Any help would be greatly appreciated.
Looks like an issue with Quartus IP generation for ModelSim simulation. Looks like its still isn't fixed. You will need to comment out the sclr port and run the simulations for now.
For LPM_MULT IP-Core asynchronous clear, clock enable & synchronous clear are have optional support so either you comment those signals or instantiate an LPM_MULT function without the squaring function and use the same signal for both dataa and datab inputs since in squaring operation multiply 'dataa' input by itself.
refer the below solution & user guide,
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
(This message was posted on behalf of Intel Corporation)