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MichaelB
New Contributor I
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Quartus 19.2 issue placing IO PLL clock pins for HBM2

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Hi,

I'd like to place the reference clock pins for the IO PLL for both HBM2s available on Stratix 10 1SM16BEU2F55E2VG.

I have assigned the reference clock for top HBM2 to PIN_BA35 and for bottom HBM2 PIN_U35.

I have connect the input port directly to my QSYS system where the HBM2s are instantiated - is this maybe invalid?

 

In .qsf file the settings are applied as in the HBM2 example design provided by Intel:

set_location_assignment PIN_BA35 -to hbm2_pll_bottom_refclk_i
set_location_assignment PIN_U35 -to hbm2_pll_top_refclk_i

set_instance_assignment -name IO_STANDARD LVDS -to hbm2_pll_bottom_refclk_i -entity hbm2_toplevel
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to hbm2_pll_bottom_refclk_i -entity hbm2_toplevel
set_instance_assignment -name IO_STANDARD LVDS -to hbm2_pll_top_refclk_i -entity hbm2_toplevel
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to hbm2_pll_top_refclk_i -entity hbm2_toplevel

 

I receive the following error in Fitter Plan stage:

Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. 
Error(175020): The Fitter cannot place logic pin in region (11, 2) to (11, 2), to which it is constrained, because there are no valid locations in the region for logic of this type. 
Info(14596): Information about the failing component(s): 
Info(175028): The pin name(s): hbm2_pll_bottom_refclk_i 
Error(16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below: 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_BA35 
Info(175015): The I/O pad hbm2_pll_bottom_refclk_i is constrained to the location PIN_BA35 due to: User Location Constraints (PIN_BA35) 
Info(14709): The constrained I/O pad is contained within this pin 
Error(175020): The Fitter cannot place logic pin in region (11, 292) to (11, 292), to which it is constrained, because there are no valid locations in the region for logic of this type. 
Info(14596): Information about the failing component(s): 
Info(175028): The pin name(s): hbm2_pll_top_refclk_i 
Error(16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below: 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_U35 
Info(175015): The I/O pad hbm2_pll_top_refclk_i is constrained to the location PIN_U35 due to: User Location Constraints (PIN_U35) 
Info(14709): The constrained I/O pad is contained within this pin 
Error(175020): The Fitter cannot place logic pin in region (11, 2) to (11, 2), to which it is constrained, because there are no valid locations in the region for logic of this type. 
Info(14596): Information about the failing component(s): 
Info(175028): The pin name(s): hbm2_pll_bottom_refclk_i 
Error(16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below: 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_BA35 
Info(175015): The I/O pad hbm2_pll_bottom_refclk_i is constrained to the location PIN_BA35 due to: User Location Constraints (PIN_BA35) 
Info(14709): The constrained I/O pad is contained within this pin 
Info(14596): Information about the failing component(s): 
Info(175028): The pin name(s): hbm2_pll_bottom_refclk_i 
Info(175028): The pin name(s): hbm2_pll_bottom_refclk_i 
Error(16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below: 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_BA35 
Info(175015): The I/O pad hbm2_pll_bottom_refclk_i is constrained to the location PIN_BA35 due to: User Location Constraints (PIN_BA35) 
Info(14709): The constrained I/O pad is contained within this pin 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_BA35 
Info(175029): pin containing PIN_BA35 
Info(175015): The I/O pad hbm2_pll_bottom_refclk_i is constrained to the location PIN_BA35 due to: User Location Constraints (PIN_BA35) 
Info(14709): The constrained I/O pad is contained within this pin 
Info(14709): The constrained I/O pad is contained within this pin 
Error(175020): The Fitter cannot place logic pin in region (11, 292) to (11, 292), to which it is constrained, because there are no valid locations in the region for logic of this type. 
Info(14596): Information about the failing component(s): 
Info(175028): The pin name(s): hbm2_pll_top_refclk_i 
Error(16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below: 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_U35 
Info(175015): The I/O pad hbm2_pll_top_refclk_i is constrained to the location PIN_U35 due to: User Location Constraints (PIN_U35) 
Info(14709): The constrained I/O pad is contained within this pin 
Info(14596): Information about the failing component(s): 
Info(175028): The pin name(s): hbm2_pll_top_refclk_i 
Info(175028): The pin name(s): hbm2_pll_top_refclk_i 
Error(16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below: 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_U35 
Info(175015): The I/O pad hbm2_pll_top_refclk_i is constrained to the location PIN_U35 due to: User Location Constraints (PIN_U35) 
Info(14709): The constrained I/O pad is contained within this pin 
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 
Info(175029): pin containing PIN_U35 
Info(175015): The I/O pad hbm2_pll_top_refclk_i is constrained to the location PIN_U35 due to: User Location Constraints (PIN_U35) 
Info(14709): The constrained I/O pad is contained within this pin 
Info(175029): pin containing PIN_U35 
Info(14709): The constrained I/O pad is contained within this pin 
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. 
Error(16297): An error has occurred while trying to initialize the plan stage. 

 

Do you have any hint how to solve this error?

Are those pins valid for IO PLL used for HBM2?

 

Best regards,

 Michael

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1 Solution
yoichiK_intel
Employee
231 Views

Hi Michael

 

BA35 and U35 is reference clock for eSRAM.  Please check the pin out file for the UIB_PLL_REF_CLK pin locaton for HBM2 pll_ref_clk

Here is the pin placement guideline for HBM2 pll_ref_clk  pin

Place this reference clock input on the
UIB_PLL_REF_CLK_00 pins while using
the HBM2 device on the bottom of the
FPGA, or the UIB_PLL_REF_CLK_01
pins while using the HBM2 on the top
of the FPGA.

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yoichiK_intel
Employee
232 Views

Hi Michael

 

BA35 and U35 is reference clock for eSRAM.  Please check the pin out file for the UIB_PLL_REF_CLK pin locaton for HBM2 pll_ref_clk

Here is the pin placement guideline for HBM2 pll_ref_clk  pin

Place this reference clock input on the
UIB_PLL_REF_CLK_00 pins while using
the HBM2 device on the bottom of the
FPGA, or the UIB_PLL_REF_CLK_01
pins while using the HBM2 on the top
of the FPGA.

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