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Quartus 22 - University Program VWF - Ouputs stays to an undefined state

rva1311
Beginner
1,807 Views

Hi,

 

I try to use Quartus 22.1 on Linux for the target 5CSEBA6U23I7.

 

Simulations work when I use Tool > Run Simulation Tool > RTL Simulation.

 

But when I want to simulate a University Program VWF, outputs stays to undefined on the window which popups at the end of the simulation.

 

Is it a common issue ?

 

Best regards

 

 

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11 Replies
IntelSupport
Community Manager
1,766 Views

Have you established any output in the waveform window?

You may need to add node for output using node finder by right click --> insert node or bus --> choose your input/output

Any snapshot on the issue maybe if possible? 


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rva1311
Beginner
1,747 Views

Yes I had added each input/output before to launch the simulation. The output stays just to undefined.

 

 

Capture d’écran de 2023-03-07 14-57-48.jpg

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sstrell
Honored Contributor III
1,735 Views

Without seeing the design, there's no way to know what's going on here.  Can you provide the code?

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rva1311
Beginner
1,721 Views

Here the used code.

library ieee;

use ieee.std_logic_1164.all;

entity pmu is
	port(
		clk : in std_logic;
		rst : out std_logic
	);
end pmu;

architecture rtl of pmu is

begin

	rst <= not clk; 

end rtl;

 Thank you for your help.

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IntelSupport
Community Manager
1,713 Views

Hi Remy,


From the snippet code given, the output of the rst signal will stay at an undefined state during because it is being driven by a combinational logic circuit that depends on the clk input signal.


To fix this issue, you can use an initial value for the rst signal in the architecture. For example, you can add a default initial value of '0' to the rst signal declaration, like this:


entity pmu is

port(

clk : in std_logic;

rst : out std_logic := '0' -- add default initial value

);

end pmu;


architecture rtl of pmu is

begin

rst <= not clk; 

end rtl;


This will ensure that the rst signal is initialized to a known value at the beginning of the simulation, preventing it from being in an undefined state.


p/s: If any answer from the community or Intel Support are helpful, please feel free mark and solution, give kudos and rate 5/5 survey.



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rva1311
Beginner
1,706 Views

As I said in my first message:

 

"Simulations work when I use Tool > Run Simulation Tool > RTL Simulation. The issue appears only when I use University Program VWF, outputs stays to undefined on the window which popups at the end of the simulation."

 

So I have already verified if it is a VHDL issue and it is not. For example, even if I put:

architecture rtl of pmu is

begin

	rst <= '1'; 

end rtl;

this changes nothing...

 

For me, it is a tool issue. It seems there is a communication issue between the simulator and the viewer.

 

I just want to know if it is a known issue and if there is a solution.

 

Thank you for your help.

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Azimath
Beginner
1,662 Views

Hello. I have the exactly same problem with vwf simulation in quartus 22.1 on linux.
The output stay X after I "Run a functional simulation".
Note that i remove the -novopt option in order to make it run without error. i don't know whether this matter or not to the stay X problem.

note that in 2nd image i send. That the right window's "Run Functional Simulation" gray out. Indicate that is simulation result.

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IntelSupport
Community Manager
1,641 Views

Hi Remy,


Seem there is issue with VWF tool, I will report this to developer for fix. 

Is using Modelsim simulation work for you? 


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Azimath
Beginner
1,640 Views

Yes, I think it works fine.

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boingbumtschak
Beginner
189 Views

Good morning,

Any update on this issue with VWF tool? Have developers fixed it?

I am using Quartus Prime 23.1 and I have the same behavior

Thank you

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IntelSupport
Community Manager
1,624 Views

Glad that is working fine. Let me know if there is any other concern


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