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Quartus 23.2 crashes on fitter : Internal Error: Sub-system: PTI

jdes
Novice
1,992 Views

Hello,

Quartus is repetitively crashing during the fitting stage with the following error :
```
Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder_nightfury_hssi.cpp, Line: 451
Found fpll 34 which has clock output O_CLK0, but its timing netlist is missing its feedback loop
```
I am targeting the `10CX150YF780E5G` part.

I am a little lost as to how to what is causing this.

I have attached the crash and fitter log.


System information :


Quartus : Version 23.2.0 Build 94 06/14/2023 SC Pro Edition
OS : 18.04.1-Ubuntu SMP

Thanks in advance

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11 Replies
SyafieqS
Employee
1,965 Views

Do you mind to attach the design for me to replicate?


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jdes
Novice
1,948 Views

Hello,

Thank you for getting back to me.

The attached archive should contain all design files.

Alternatively the project is available on github : 
https://github.com/Essenceia/ethernet-physical-layer
sha1 : 4b2dfac0fd23dcc6315a09f9e843b0a855e9ea9f

To reproduce my exact build flow which triggers this crash  :
```
cd tcl
make place_PCS
```

This build flow will setup the quartus project, generate the IP's and launch the full flow ( `execute_flow -compile` ) , which will then fail during the fitter stage.

Additionally, I have confirmed the failure can also be reproduced when launching manually from quartus.

I will be happy to provide any additional files if required.

Best regards

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SyafieqS
Employee
1,896 Views

Thank you. Let me take a look at the design to reproduce and let you know any update.


SyafieqS
Employee
1,826 Views

Hi Julia,


Is it possible for you to compile in latest release? 23.3?

New version has lot of bug/fix. Let me know.


jdes
Novice
1,816 Views

Sure thing, let me download that and get back to you.

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SyafieqS
Employee
1,795 Views

Anyway I am able to verify the issue at my end. I am further looking this and parallelly forward this to developer for fix/wa


SyafieqS
Employee
1,728 Views

Did you able to verify this on 23.3?

Is the issue still persist?


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jdes
Novice
1,695 Views

Hello,

Yes, unfortunately the issue still persist with quartus 23.3.
You will find the error report attached to this post.

The tcl for generating the transceiver IP wasn't compatible so I has to update it.
For your testing purposes you can find the 23.3 compatible version at sha1 : 21f8f91e5e993bd2a69715e99478acdbcdf1c7e8.
( https://github.com/Essenceia/ethernet-physical-layer )

Best regards

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SyafieqS
Employee
1,642 Views

Noted. I have filled bug for a fix.

Will let you know any update


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SyafieqS
Employee
1,574 Views

Hi Julia,


Update:


The issue appears to occur when is_pa_core (is phase aligned to core) is set to "true", which enables feedback compensation via iqtxrxclk wires. However, this mode doesn't have a valid feedback timing model, so is_pa_core can only be set to "false". A possible workaround would be to disable is_pa_core and the iqtxrxclk parameters. Try editing phyfpll/synth/phyfpll.v and change these 3 parameters:


is_pa_core from "true" to "false"

cmu_fpll_pll_iqclk_mux_sel from "iqtxrxclk0" to "power_down"

cmu_fpll_fpll_iqtxrxclk_out_enable from "fpll_iqtxrxclk_out_enable" to "fpll_iqtxrxclk_out_disable"


I am able to pass the flow with the workaround. Please validate this at your end and let me know any update.

The fix will be planned soon.


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SyafieqS
Employee
1,525 Views

No response from the customer after the answer being provided: As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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