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Quartus/Chip Planner: How can I lock in design and simply change clock speed?

tschesnok
Beginner
224 Views

I have the following problem meeting timing on a Max10 (M02):

 

I have a design resolving to 90% utilization. Uses a PLL (dual clocks in system)

 

When the "fast" clock is set to 234 mhz I get a fast clock FMax of 243 mhz and everything meets timing. If I increase the PLL to 243.. or any number between 230-243 I get a drop in FMAX to below 225 and the design does not meet timing. Everything else remains unchanged. (Same is true for any other random immaterial change in the code.. I get a random FMAX changes in the 20-30mhz range)

 

This feels like a design utilization / chip layout issue.

 

I hate to leave 10 mhz on the table.. since the design can technically run at 243. Is there a way to lock in the design/layout at 234 mhz (using chip planner).. and then simply change the PLL speed to 243mhz?

 

I'm a beginner to intermediate user on Altera tools.. so I don't know anything...

PS - design compiles using best area / best performance settings.

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sstrell
Honored Contributor III
182 Views

Fmax is not gospel.  It's an estimate of what the potential maximum frequency of the currently placed and routed design *should* be able to run at.  There's no guarantee that it will.  That Fmax may be just at the cusp of 0 ns of slack somewhere.  You use Fmax to say, OK, in the future, I can try adjusting my design to run at this speed and the Fitter should be able to provide me a design that works at that speed (though no guarantees if you're pushing it).

If you increase the speed of your design by changing the PLL settings and your .sdc file, the Fitter will run in a different way to make sure the design meets timing at that speed (if it can), then reporting on an Fmax that *may* be faster than what you are running at.  In other words, the Fitter gives you what you ask for.

As for locking down the design, the Standard edition of Quartus does include the incremental compilation feature, which lets you lock down and reuse the post-fit netlists of parts of your design you designate (called design partitions).  This is useful for timing closure in a large design because you can close timing in just a part of the design and then lock it down (and continue locking down partitions as you get them to close timing) so it doesn't change the next time you compile.  However, I don't think this is really what you are looking for.

In other device families, you can change PLL settings during runtime (dynamic PLL), but that's not available in MAX 10 devices.

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7 Replies
tschesnok
Beginner
206 Views

Is this even possible with the free edition?

 

Nurina
Employee
202 Views

Hi,


As you increase the target Fmax, timing requirements is harder to meet and the optimal place & route to meet timing will be different.

That being said, locking down the design at 234MHz before changing the PLL target Fmax won't help.


Can you share the Report Timing from Timing Analyzer?


Which Quartus version are you using?


Regards,

Nurina


tschesnok
Beginner
194 Views

Thanks for your reply. I'm using 20.1.0 lite. (I would give you more detail.. but Quartus (like many other times) will not let me cut and paste it)

 

I'm confused. If my design is fully constrained.. with a clock defined at say 100 mhz.. and it results in meeting timing with an FMAX of 120 mhz.. are you telling me that I CAN'T run that design at 120mhz? What is the point of FMAX?

 

I'm suggesting the fitter is stupid.. it creates a high performance solution (but at the wrong PLL settings). When I change the PLL to match the fitting performance.. the fitting changes and gets worse. 

 

Put another way.. (and this also happens) Let's say the design does NOT meet timing at 220 mhz.. but suggests (via FMAX) that it will meet timing at 200 mhz.. if I relax the clock to 200Mhz.. guess what.. my new FMAX is suddenly 180 mhz and it still fails...

 

Bottom line.. fitter sucks and it needs manual help. If I can't lock down the design with the free version of quartus.. well.. I'm out of luck since I'm not paying. I have not seen these erratic placer issues with Xilinx. 

 

 

sstrell
Honored Contributor III
183 Views

Fmax is not gospel.  It's an estimate of what the potential maximum frequency of the currently placed and routed design *should* be able to run at.  There's no guarantee that it will.  That Fmax may be just at the cusp of 0 ns of slack somewhere.  You use Fmax to say, OK, in the future, I can try adjusting my design to run at this speed and the Fitter should be able to provide me a design that works at that speed (though no guarantees if you're pushing it).

If you increase the speed of your design by changing the PLL settings and your .sdc file, the Fitter will run in a different way to make sure the design meets timing at that speed (if it can), then reporting on an Fmax that *may* be faster than what you are running at.  In other words, the Fitter gives you what you ask for.

As for locking down the design, the Standard edition of Quartus does include the incremental compilation feature, which lets you lock down and reuse the post-fit netlists of parts of your design you designate (called design partitions).  This is useful for timing closure in a large design because you can close timing in just a part of the design and then lock it down (and continue locking down partitions as you get them to close timing) so it doesn't change the next time you compile.  However, I don't think this is really what you are looking for.

In other device families, you can change PLL settings during runtime (dynamic PLL), but that's not available in MAX 10 devices.

tschesnok
Beginner
170 Views

Thank you. This explanation is helpful. 

Nurina
Employee
135 Views

Hi,


Does the above reply help?


Regards,

Nurina


Nurina
Employee
108 Views

Hi,


We do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina


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