Quartus II 12 Web Edition + ModelSim Altera = output pins are always in 'X' state

[Altera_Forum]

Hello! 

I tried to follow few tutorials on the internet on how to use Quartus + Modelsim, but no matter what I do in the end simulation does not work correctly - all output pins are always in 'X' state. The only situation when they are not in 'X' state is when they are connected directly to vcc or gnd, but if they are connected to the output of some logic element or to an input pin - they stay in 'X'.  For example, I start new Quartus project for maxII, add schematics file, draw some simple scheme, assign pins:  https://www.alteraforum.com/forum/attachment.php?attachmentid=6730   It compiles, but with few warnings (like feature logiclock is disabled due to the licence etc.) then I start gate level simulation. ModelSim opens, I choose 'start simulation' from the menu, choose maxii_ver library, choose my design as top-level and press ok. Then I add clock signal to the input pins and do simulation for few ps and this is what I get:  https://www.alteraforum.com/forum/attachment.php?attachmentid=6731   It also happens in example designs that I've found and it happens when I create a megafunction. When I simulate the same logic written in verilog in ModelSim it works correctly, but Quartus designs do not.  What may be wrong or what am I missing?  Update: tried to do the same using VHDL and it works correctly! But since Verilog is my main hdl I want to find the solution to the problem with it.  Update2: tried to do simulation in Active-HDL SE - works fine with verilog. I guess I'll stick with it then.

[Altera_Forum]

Have you solved the problem using Modelsim Altera? Else, I might be able to help you.