I made a change to my FPGA SystemVerilog project which has caused Analysis & Synthesis to become stuck.
Unfortunately I have lost my undo history after restarting Quartus so I cannot revert back to what I had.
Can you please help me resolve this issue and advise of any logs you may require. I'll make a copy of this project and keep it for further investigation.
Is your previous design can be compiled before you make the changes? Yes, there is limitation for language support when using SystemVerilog on Quartus Prime Lite according to the link below and this could be one of the reason that it stuck when you call these functions
-> function void DoMainMenu;
-> function byte getStr( byte promptIdx );
Hi. Sorry, I thought I'd cancelled this question. Anyway.. after further investigation I believe the compiler freezing was caused by the for() loop in my design. Because I'm a software developer, I keep making the same mistake of trying to implement solutions as I would in C. I believe the use of non-constant variables in the for() loop is what caused this freeze. I reckon the complexity of the design confuses the compiler and ultimately causes it to lock up.
Now that I've moved away from the use of the for() loop and I've implemented a state machine, my code compiles so much faster.
To answer your question though, yes, my code did compile before I made changes. Unfortunately I don't know for sure what the code looked like before I made the changes because I restarted Quartus and therefore lost the undo/redo history.
So lesson learnt: stay away from for() loops and use state machines instead.. and stop passing 255 byte arrays around as ports - ie - think of all modules as chips in an an 8-bit computer.