Quartus II Analysis and Synthesis Issues

[Altera_Forum]

I have a strange issue with some code I'm working with. I received a Quartus project from TI that should, supposedly, work out of the box. In fact, on the machine running Quartus 2 v13, the code compiles and synthesizes. However, I have a different computer running Quartus 2 v14, and I get syntaxical errors when I try to compile on that machine. The errors look like: 

 10170 Verilog HDL syntax error at adcif.v(115) near text ")"; expecting an operand 10170 Verilog HDL syntax error at adcif.v(120) near text "begin"; expecting an identifier ("begin" is a reserved keyword ) ...  The thing is, this same project without change was previously running analysis and synthesis on the v14 machine, and is *still* running analysis and synthesis fine on the v13 machine. I unpacked the project file again to make sure I was running it without change. Are there any strange issues or settings with Quartus 2 that could cause this kind of behavior?  I've attached the .qar file, I'd love to see if someone else can run analysis and synthesis without changes to the code (or report if they hit errors)?

[Altera_Forum]

It seems to be some syntax issue with the .v file. Just wonder if you can try with the latest QII 15.0 to see if it helps?

[Altera_Forum]

I just ran you Qar with Quartus 14.0.0 build 200 and the project completed (with 0 errors, 58 warnings and 346 info lines). (Timining is not clean but it built). 

 This was the linux version, but should match what you did.  I was going to run it in 15.0.2, but I don't have the Stratix IV device family installed at the moment. So either the adcif.v file got accidentally modified or it's a weird 14.0 windows issues.  Pete

[Altera_Forum]

I get identical results to Pete when running it, unmodified, through Quartus 14.1.0 build 186 on Windows 7. 

 I can cause the Quartus to generate similar errors (and a lot more - can I assume you've just pasted the first couple into your post?) by changing the compiler settings Verilog version to Verilog-1995. You might check that, although that is part of the project settings and not your installation.  A long shot but licensing issues often show up in strange ways. You might want to check that. Other than that re-installing v14 doesn't take long although, again, I'm not sure I'd necessarily expect much from that. Or v14 on another machine...?  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  I can cause the Quartus to generate similar errors (and a lot more - can I assume you've just pasted the first couple into your post?) by changing the compiler settings Verilog version to Verilog-1995. You might check that, although that is part of the project settings and not your installation.  --- Quote End ---    Can you perhaps instruct me on how to change compiler? Perhaps I can simply make that change and have it work for my purposes. I *am not* a Quartus or even FPGA guru.    --- Quote Start ---  A long shot but licensing issues often show up in strange ways. You might want to check that. Other than that re-installing v14 doesn't take long although, again, I'm not sure I'd necessarily expect much from that. Or v14 on another machine...?  --- Quote End ---    If nothing else works I'll certainly try this, my only concern is that this *is* a fresh install, and I'd hate to have the same issue keep coming back!  Thanks again for your help!

[Altera_Forum]

With your project open, go to 'Assignments' -> 'Settings...'. In the left pane, under 'Compiler Settings', select 'Verilog HDL Input'. Then, in the right pane, you can choose the verilog version. 

 Cheers, Alex