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Valued Contributor III

Quartus II & Max7000 Jtag Issues


I've what I thought was an easy Project in designing some logic for a EPM7128SLC Device. This is so I can use the logic to test a PCB I'm repairing. 

After Installing Quartus II (Web Version) 13.0 SP1, designing the logic & running the compiler. 

I'm receiving Fitter error messages relating to Input Pins (that i need to use these Inputs on the JTAG Pins) that are connected to all 4 JTAG Pins . 

""Error (163043): Pin "A1" is assigned to JTAG pin PIN_14, but the pin already drives a JTAG pin" etc etc. 

If I go into device pin options from the Assignments Menu and disable "Enable JTAG BST support" then the logic will compile without issues. 

However, the only way I can program this device at present is with a JTAG usb blaster & if i disable the JTAG BST support i can't open the programmer from within Quartus II. 

Alternatively I've tried generating the aasembler files as hex files, but these are greyed out from the programming options. 

Another workaround I tried was converting the .pof file to hex, but the compiler doesn't create any SRAM (.sof) files for me to input into the Convertor. 

Any help would be apprecisted. 


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Valued Contributor III

Is this a pretty old design? I suspect you have a design which relied on a stand alone programmer to configure the CPLD before it was assembled onto the PCB. MAX7000S devices could be programmed using a number of different programmers, made by both Altera and third parties. If the JTAG pins have been put to use as part of the original design then, I suspect, the device was originally programmed in such a manner. 


Refer to the, pretty ancient, "altera programming hardware (" document. 



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