Quartus II beta - WYSIWYG error

Altera_Forum · ‎09-17-2007

Hi

I am trying to compile a design in Quarus II 7.2 beta with the following components:

- Nios CPU

- JTAG

- Onchip memory

- DDR SDRAM High performance controller

- timer

I keep getting this error and I cannot figure out how to fix it:

I do not get this error in Quarus 7.1 where the design compiles without any problems. I know that it is a beta version of 7.2 I am using, but does anybody know how to fix this?

If I double click on the error then I get to this line:

ddio_outa[0..0] : cycloneiii_ddio_out

WITH (

async_mode = "none",

power_up = "low",

sync_mode = "none",

use_new_clocking_model = "true"

);

in the file

db/ddio_bidir_cmg.tdf

Any ideas?

Thanks

Best Regards

Tom

Altera_Forum · ‎09-17-2007

I have gotten that error in both version 7.1 and version 7.1 SP1 copies of a Cyclone III design using the DDR2 SDRAM High Performance Controller. Both times I was editing the design without simultaneously changing the Quartus or DDR2 IP version. If you changed the design at the same time you changed Quartus versions, the error might be from the design change and not a 7.2 beta problem. (I never debugged my error cause. I always tried something else that kept me from having to do anything about the error.)

In case your error was just from upgrading to the beta, I tried recompiling a 7.1 SP1 version of my design using 7.2. I first compiled it without regenerating the DDR2 MegaCore with 7.2; the MegaCore files were the ones from 7.1 SP1. I compiled with no error. I next compiled it after regenerating the MegaCore with 7.2. That also compiled with no error. Of course, my result doesn't rule out a 7.2 beta problem with your design. At least one difference between our designs is that mine does not use SOPC Builder.

If you just upgraded the Quartus version without editing anything (or if you can reproduce your error by starting again with a copy of your 7.1 design and just upgrading the version), that probably is supposed to work for your design like it did for mine. I'm not as confident about this, but I expect that you also should be able to recompile a 7.1 design in 7.2 if you regenerated your SOPC Builder system (which probably regenerated the DDR MegaCore). If you know your error isn't from a design change, please file a service request so that Altera can determine whether there is a 7.2 problem with upgrading existing designs without any unintended extra user effort.

Altera_Forum · ‎09-18-2007

Hi Brad

Thanks for your reply.

I have tried to open the design in 7.2 beta and the compilation runs fine, but if I regenerate the SOPC builder system then I get the error. I have filed a service request as I believe it is a problem in 7.2 beta. I have also tried to generate a new system in 7.2 beta and I get the same error again. I guess I will just have to wait for the final 7.2 version.

Regards

Tom

Altera_Forum · ‎09-19-2007

Are you using 7.2 version beta of all the tools, i.e., (Quartus II, IP Megacore and Nios II) ? Or Quartus II v7.2 beta and rest are v7.1?

Altera_Forum · ‎09-20-2007

I am using 7.2 beta for all tools.

Regards

Tom

Altera_Forum · ‎09-21-2007

I suspect that it might be Cyclone III compatibility issue (Device support) (assuming that device being targeted is Cyclone III). In any case, it would be better to file an SR to Altera for this issue.

Altera_Forum · ‎09-25-2007

The error was not a bug in Quartus II 7.2 beta, but an error in my own design.... I had not noticed that the sdram_clk and the sdram_clk_n are both bidirectional. When this error is fixed the design compiles. I have not tested the design on my board yet, but hopefully everything works....

Regards

Tom