Quartus II newbie questions

[Altera_Forum]

Hello, 

I recently installed the latest Quartus II 8.0 SP1 and I am trying to get familiar with the tool. I have few questions I couldn't find an answer in the tutorials or by searching. 1. How I can generate a VHDL instantiation template? The File->Create/Update->Create VHDL Component... does only the component declaration. 2. I created a minimal test design with two VHDL files , one of them being the top module. What I noticed is that "Analyze Current File" always analyzes both of them,no mather which one I am currently working on. Why? I did not instantiated (yet) the second module in the top entity. 3. How I can generate a test bench template for a file other than the top module? (Simulation tool: Modelsim-Altera) Processing->Start->Start Test Bench Template Writer always generates the test bench for the top module.  General comments. I thought this tool would be a friendly one. But I find important commands or options deeply hidden under misleading menus and hard to use. But maybe it's just me, being new with Quartus. Thanks! BR

[Altera_Forum]

Hi, 

 1. I couldn't find, either. Probably there is no such template.  2. Are these files shown in the file list, which is located Project->Add/Remove Files...  3. You can change the top module in your project from General categoly in the setting dialog box. Once you set any module as a top, you can create testbench for it.  I hope this answer can help.  Thanks,

[Altera_Forum]

1) You need to have a VHDL file open in Quartus 

Use   Edit->Insert Template->Constructs->Design Units-> Entity  and  Edit->Insert Template->Constructs->Design Units-> Architecture  To generate a VHDL entity and architecture  2) Are you certain you are not seeing messages relating to the component instantiation rather than actucal analysis of the sub module?  3) You could try temporarily making the sub-module the top level and making a testbench for that.   Hope this helps a bit

[Altera_Forum]

Thank you gee, 

1. Well, there is "Create Verilog Instantiation Template" under the same menu. Why not VHDL too? So, when you have a complex component with many pins how do you instantiate it? You manually type it? 2. Both files are present in Project-> Add remove files. 3. Yes, true. But this is weird...

[Altera_Forum]

Hi vernmid, 

Thank you for the answer. 1. This is not what I want. I want an instantiation template for my component, not a generic, empty one. 2. I have quite good VHDL experience. I don't have any error in my files actually. But when I deliberately introduce an error in one file (like one line containing the "-" only), save it, then go to the other file and click Analyze Current File, it gives me the error for the other file (which is not current!) 3. Yes, thank you. I don't think this is how it should be!

[Altera_Forum]

Hi, 

 1. It is inconvenient but ... 2. Don't you try to remove the file you don't want to elabolate?

[Altera_Forum]

You could try 

 http://www.vhdl-online.de/tb-gen/ent2tb1.htm  Hope this is more like what you were after

[Altera_Forum]

I don't understand. If I create a VHDL file, then use Edit->Insert Template. There are more options and templates under VHDL than I can even wrap my head around. 

 For a component declaration, all you have to do is drop in the template. Then start double clicking on the fields and replacing them with your signal names and such.   Most people don't use code generators to create their VHDL or Verilog port lists. There is really only one platform where I know this is done and that is ISE.   I mean you're likely going to spend hours inside that module writing code. An extra 2 minutes to create a port list should be insignificant.  Altera's Quartus II documentation is quite through and covers all of the options for synthesis, place and route, etc. If you haven't taken the time yet to study the documentation, you should.

[Altera_Forum]

Hi jakobjones, 

Well, thank you for the answer. But you see, yes you can type your ports in 2 minutes for one module, but a real design usually has more than one. And yes, ISE does this. From what I see, Quartus does this also but for Verilog only. Don't you think this is a bit inconsistent (providing a feature for Verilog but not for VHDL)? And thank you for pointing to the documentation, but the questions here were not about "options for synthesis, place and route, etc". How about the other inconsistencies I asked in my initial post? Are there answers in the documentation about them? Thank you for helping! BR

[Altera_Forum]

1 - I believe if you were to look at my code you would find it to be anything but simple. I personally can type a port list by hand faster than using the ISE generator so I don't have much use for it. 

 2 -   --- Quote Start ---  General comments. I thought this tool would be a friendly one. But I find important commands or options deeply hidden under misleading menus and hard to use.  --- Quote End ---   I apologize, by this statement I thought you were referring to the the intricacies of Quartus' options which is why I referred you to the documentation.   3 - By inconsistencies I believe you mean "doesn't behave like ISE". What version of Quartus II are you using?  a - Edit->Insert Template->VHDL->Constructs->Design Units->Entity (Is this not what your are looking for?). I realize it's not the same as the ISE module generator but does it meet your needs.  b - When I click on the "Analyze Current File" button on the left side of the text editor window (I normally use an external editor so this is new to me), It only analyzes the currently open file and no others.  c - Sorry I do all of my simulation directly in ModelSim so I can't field this one.   Look I use both Xilinx and Altera products and software. There are advantages to each. From your comments it appears you are very comfortable with ISE and that's probably what you have used for most of your career. No problem. I personally have found Altera's software to be superior to what Xilinx offers for reasons I won't mention here. I still use both and they both still work. Quartus II is not ISE.    I have tried to develop my design flow and methods so that I can easily transition between multiple design environments without being too dependent on each environment's unique behaviors.   Even if you remain a hard-core Xilinx user, you are going to have to adapt your flow. ISE will be replaced over the next few years with PlanAhead which at this point is substantially different from ISE. PlanAhead incorporates features that have been found in Quartus II for several years now so this is a good step for Xilinx.   I apologize for offending you. If there is something I can do to help reduce your learning curve, let me know.  Jake

[Altera_Forum]

Jake, 

I really appreciate the time you are taking to answer here. But it seems that this discussion is not going anywhere.   --- Quote Start ---   By inconsistencies I believe you mean "doesn't behave like ISE"  --- Quote End ---  I don't think I ever said or inferred that Quartus should behave like ISE. I actually did not mentioned Xilinx or ISE before you did.   --- Quote Start ---  What version of Quartus II are you using?  --- Quote End ---  I mentioned in the initial post:   --- Quote Start ---  I recently installed the latest Quartus II 8.0 SP1  --- Quote End ---  When I say inconsistencies I really mean inconsistencies with Quartus itself: 1. Instantiation template for Verilog but not for VHDL. Does it have to be ISE to treat both languages equally? 2. I thought "Analyze Current File" really means analyzing only the current file (and the modules instantiated in it). I was looking for clarification. What's wrong with this? Does it have to be ISE to do what it says? 3. Is it ISE'ish to be able to generate a test bench template for any module in a project?  Look, I understand you are a very experienced user, but not everyone is like you. Different people prefer different ways of doing the same thing (more or less productive).   --- Quote Start ---  If there is something I can do to help reduce your learning curve, let me know.  --- Quote End ---  The best way to help is to discuss about what was asked and provide a solution or work around if possible. Assuming things is usually not productive.  Thank you! BR

[Altera_Forum]

--- Quote Start ---  The best way to help is to discuss about what was asked and provide a solution or work around if possible.  --- Quote End ---    Well let's try this again.  1st question:   --- Quote Start ---  1. How I can generate a VHDL instantiation template? The File->Create/Update->Create VHDL Component... does only the component declaration.  --- Quote End ---   From Quartus beginning at the edit menu: a - Edit->Insert Template->VHDL->Constructs->Design Units->Entity. Does this menu exist in the web edition of the software and if so does it meet your needs? In my subscription edition it creates the following: entity <entity_name> is generic ( <name> : <type> := <default_value>; ... <name> : <type> := <default_value> ); port ( -- Input ports <name> : in <type>; <name> : in <type> := <default_value>; -- Inout ports <name> : inout <type>; -- Output ports <name> : out <type>; <name> : out <type> := <default_value> ); end <entity_name>;   2nd Question:   --- Quote Start ---  2. I created a minimal test design with two VHDL files , one of them being the top module. What I noticed is that "Analyze Current File" always analyzes both of them,no mather which one I am currently working on. Why? I did not instantiated (yet) the second module in the top entity.  --- Quote End ---   When I click on the "Analyze Current File" button on the left side of the text editor window (I normally use an external editor so this is new to me), It only analyzes the currently open file and no others. Here is the processing output in Quartus: Info: ******************************************************************* Info: Running Quartus II Analyze Current File Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version Info: Processing started: Wed Oct 29 17:29:43 2008 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off trio_top -c trio_top --analyze_file=C:\Projects\cvs_test\trio\fpga\X2\trio_top\src\sdi\sdi_top.v Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings Info: Peak virtual memory: 155 megabytes Info: Processing ended: Wed Oct 29 17:29:44 2008 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Can you post the output you get in the web edition?  Jake

[Altera_Forum]

1. 

  --- Quote Start ---  In my subscription edition it creates the following:  --- Quote End ---  Thank you, this is indeed a work around for the question I asked. But, honestly, it is faster for me to type it and copy/paste ports than going through a 6 levels menu+trees just to get an example about how it should look like. 2.   --- Quote Start ---  Can you post the output you get in the web edition?  --- Quote End ---  Sure, here:  Info: ******************************************************************* Info: Running Quartus II Analyze Current File Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition Info: Processing started: Wed Oct 29 19:58:27 2008 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test1 -c test1 --analyze_file=R:\altera\test1\hdl_src\my_and.vhd Error (10500): VHDL syntax error at test1.vhd(11) near text "-"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" Error (10523): Ignored construct test1 at test1.vhd(12) due to previous errors Error: Quartus II Analyze Current File was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 166 megabytes Error: Processing ended: Wed Oct 29 19:58:29 2008 Error: Elapsed time: 00:00:02 Error: Total CPU time (on all processors): 00:00:02 I am posting this from home where I have 8.0 without SP1 but I get the same from 8.0 with SP1 at work. Please notice that the analyze was started with my_and.vhd and it found an error in test1.vhd. test1 is not instantiated in my_and and is a separate file. The reported error is what I deliberately introduced to show the problem. test1 is also the name of the test project in which test1.vhd is the top entity. In your report, from what I can see, you started the analyze with the top module and of course, it reported that everything is OK. How about introducing an error in the top module and start the analyze on a sub module? BR