Quartus II serdes placement error "channels cannot be placed in the same triplet"
I got a problem when I use the RapidIO IP in my Cyclone V GTD5D7 custom board. Here are some background that, I have another USER Serdes (x1) at the Serdes channel 0. And PLL at channel 1 to provide clock for user serdes, RAPIDIOX2_IP1 and RAPIDIOX2_IP2. I can pass the placement in Quartus II(13.1) when I only enable the first RapidIOX2 IP. But when I enable the second one, the placement will fail at that “Error (11687): srio_tx_data(n) is assigned to PIN_K1, srio_tx_data(n) is assigned to PIN_W3, channels cannot be placed in the same triplet.” “Error (11688): srio_tx_data(n) is assigned to PIN_K1, srio_tx_data(n) is assigned to PIN_W3, channels cannot be placed in the same quadrant.” Where the srio_tx_data and are used for the first RapidIOX2 IP and the  and  are for the second. From the chip planner, it fails once placed the first RapidIO IP. It seems the RapidIO IP is not placed at the serdes channel that I set in pin assignment. It will be so kind of you If anyone can tell me: 1. Can we put two RapidIO IP in the cyclone V GT D5D7 Chip? 2. Did I miss any rule on serdes usage which cause the failure on placement? 3. How can I force certain IP on certain serdes resource?