my Quartus II 17.0 is stuck for hours (more than 8 hours) on 47% analisys. I am compiling for Cyclone IV E (ep4ce10...).
I noticed that, in my design (a simplified MISP CPU, mono clock), if I wired the final MUX selection signal with control signal, the compile is stuck on 47%.
If I fix the select signal of final MUX to a value (eg. VCC), my design compile in few seconds. But...why?
I am trying my design also with quartus 19.1 and the problem is the same.
Assuming your machine meet all the requirement (like memory, ram etc), may I know what type and version of Quartus and OS your are using to compile? Is there any heavy background application running? Try to end the task running for moment while do the compilation.
I had the exact same analysis and synthesis stuck on 47% issue, I solved it by setting "Allow register merging" to "Off" in Compiler settings -> advanced synthesis settings.
If that doesn't work, might be worth literally toggling every synthesis setting on that page and seeing if that works. Then narrow it down to the one setting that causes the problem by toggling a half, then a quarter, ...