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Altera_Forum
Honored Contributor I
1,632 Views

Quartus-II synthesis/compile errors for Arria V device

I have been using Altera devices (Stratix, Cyclone and others) for more than 20 years. Recently our company decide to use the new Altera Arria V device. Our project has a lot math calculations of signed integers. The combinatory path can be very long. Typically from a registered value we need to do two 12-bit multiplys and 2 to 4 24-bit summation/substractions before the result is latched in the next stage flip-flop. The circuit runs with a low speed at 25MHz. 

 

After some initial learning curve, we finally ran our design in the lab. But it did not work as we expected although we tried the same RTL code in FPGAs of another vendor. I then used SignalTap to view the key signals and found something wrong in one signal (at least). By tracing it further, I found for all the inputs the design should not cause the output overflow. However the captured result did show overflow. 

 

In order for me to see more intermediate combinatory signals between the inputs to the result of that long path, I added a few debug registers, which inputs are connected to the signals I was interested without changing the original design. And then connect the output of these registers to CPU interface block so that they would not be optimized away. After doing that I have signals available for me to add to the SignalTap. To my surprise, the new compile did the calculation correctly in this path. No more overflow was observed. Then another bug showed up from other parts. I thought how could I trust the compile and then stopped trying in the lab. 

 

Then I added a setting to export a gate-level netlist for my simulator. And I run the gate-level simulation of the chip (without timing back annotation). The second day when the simulation completes, I looked in the waveforms and verified that the error is duplicated in the simulation. It does appear that Quartus-II does not do as it should. Then I extracted the small part of the chip (3 modules) into a size-reduced "chip". After this small test chip is compiled, the gate-level simulation also showed the error. I then created a test bench to run both RTL and gate-level "chips" with the same inputs. I compare the outputs and printed error if they differ. For sure I got a lot error messages. 

 

Has anyone else experienced the same issue with Arria V device comples? Has Altera come to you for the issue? 

 

Thanks.
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15 Replies
Altera_Forum
Honored Contributor I
90 Views

Hi Shuo 

 

This sounds like a bug with Quartus. I have found bugs with various tools sets in the past with Both Xilinx and Altera's tools.  

 

It sounds like you have already isolated the issue in the gate level netlist to a specific path. I would submit a test case to Altera describing the issue and send them both the original RTL and the gatelevel netlist. The more you can isolate the issue the better. (IE if you can make a simple design that still exhibits the error it's easier for them to pinpoint the problem). 

 

Of course, they'll also want to know your tool version, and will want you to be on the latest version before continuing. So if you are not already there, I would download the latest from software.altera.com and try the compile again, to see if it's been resolved. 

 

Regards 

 

Pete
Altera_Forum
Honored Contributor I
90 Views

Hi Pete, 

 

Thanks for your comments. I filed a web case with Altera. Someone out of the U.S. is looking at my case (I got reply at morning). He/She had some difficulties in re-running my test case in a different simulator. I knew it was slow from my previous experiences of the web cases. That was why I post here to see if someone got similar before me. 

 

In the mean time our local tech support (from a third company who sold Altera device to us) has reproduced the case in VCS. And they have sent the test case to Altera with their internal connections. Now it has been recognized as a synthesis error in Quartus-II. The issue now is in Altera's plate. I hope the issue is solved soon. Our project is blocked and we are waiting.
Altera_Forum
Honored Contributor I
90 Views

Hi Shuo: 

 

I'm glad your making progress with support. And you did the correct thing by having your local Altera Rep/Distributor also working on the issue.. They tend to have a more direct link to higher level factory support. 

 

I discussed this with one of my co-workers and he suggested it may be a mapping issue with Quartus and the Arria V device.  

 

You may want to target a Stratix IV device (If you can easily) that is of similar size and see if the gate level error still exists.  

 

I know this is a time consuming task, but if you are on hold it would at least give you some additional incite into the problem. If you can get quartus to do it on a small test case that is probably the most helpful for everyone involved.  

 

(support and us). If we can reproduce the issue, with quartus, that gives more weight to the support issue. 

 

Pete
Altera_Forum
Honored Contributor I
90 Views

Our distributor has already tried different device families (including Stratix) and the problem showed up, too.  

Yes. I did make a small test case and provided to our distributor. Let me see if I can put it somewhere for you to get....
Altera_Forum
Honored Contributor I
90 Views

This post has been removed.

Altera_Forum
Honored Contributor I
90 Views

Altera engineers have pointed to the cause of the problem: "The root cause of the problem has been identified. It's due to a bug in software when 2 DSP blocks are chained together AND signed numbers are used -- this will cause an error to occur." 

 

Hopefully Altera will have a fix soon.
Altera_Forum
Honored Contributor I
90 Views

Thanks for letting us know. That's a nasty one. 

 

Pete
Altera_Forum
Honored Contributor I
90 Views

I don't know if you have seen this yet or not, but Quartus 13.1 was just release and is available from software.altera.com 

 

You may want to verify this issue is corrected in this version of quartus. 

 

Pete
Altera_Forum
Honored Contributor I
90 Views

I was told that 13.1 does not have the fix for this problem. Altera has provided a patch to me. They said that the next version (maybe 13.2) will have the fix integrated.

Altera_Forum
Honored Contributor I
90 Views

Can you post the Service Request number this is under. A don't see any 13.1 dp releases yet, so I just want to be able to track what version it's corrected in. 

 

Thanks 

 

Pete
Altera_Forum
Honored Contributor I
90 Views

Hi Pete, 

 

The fix is not in any published version yet. But they promised to put in the next new version from now. 

The patch files are on our distributor web site. I do not know if you can get them. Or if they are still there. But the following are the links: (remove dashes when copy and past) 

 

Read Me: h-tt-ps://macnica.box.com/s/jt4lc2jj5i14g1lw36cb 

Windows: h-tt-ps://macnica.box.com/s/sqzsdri3qt81ilnkma9w 

Linux: h-ttp-s://macnica.box.com/s/bp161evrpejw9eqpqoj6
Altera_Forum
Honored Contributor I
90 Views

Note that the patch is to add to 13.0sp1 only. 

 

In addition to this problem I now discovered another synthesis problem in Quartus-II with nested case statement. However I have not been able to create a reduced-size test case for it. When the size is reduced the problem goes away. What I did to my design is to replace all the nested case statements with if/else statements. So far I can work around this later problem.
Altera_Forum
Honored Contributor I
90 Views

SR is 10994366

Altera_Forum
Honored Contributor I
90 Views

I am still using 13.1.0 with software patch. 

Someone else tried newer versions including 14.1. The bug is still in Quartus-II.
Juan_Miller
Beginner
88 Views

Have you tried 'long path tool'?
it's very helpful for me.

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