Quartus - Linux and Windows

[Badeskov]

Hi All,

I must admit that I am getting exceeding tired of Intel and the Quartus FPGA and SoC handling under windows. Sadly I thought this would be easy to set up, but apparent I was wrong. Admittedly, I am by no means a Linux expert, but I do know my way around. I have been doing FPGA work for 20+ years, mostly AMD (Xilinx), and a lot of embedded before (only AMD), but this is my first foray into the Intel SoC realm, and I must admit that I am not impressed. 

So, I am running 

1. Window 10 (19045.3086)

2. Quartus 22.1 std

3. Quartus SoC EDS 20.1

So, according to every installation manual I have found (and I have looked through a lot), I need to install Ubuntu 18.04 under WSL 1, so I did as per here:

https://www.intel.com/content/www/us/en/docs/programmable/683525/21-3/installing-windows-subsystem-for-linux.html

Subsequently, I did all the prerequisites here:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10

And all looks good. I can compile just fine, but being able to put the boot image on an SD card eludes me. Every method I try seemingly requires Linux running under WSL2 (ripping already sparse collection of hair out).  E.g., when doing the Yocto steps here:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Appendix_45_Building_Linux_Binaries

The step 

bitbake core-image-minimal

comes back and tells me that (through sanity.conf) requires WSL2 and when quite un-elegantly bypassing that, the subsequent builds do not work. Likewise, when following the Intel instructions here:

https://www.intel.com/content/www/us/en/docs/programmable/683435/17-1/creating-an-sd-flash-card-image.html

I run into the same issue that the /dev/loop mounting step essentially requires WSL2 as WSL1 is not a true virtualization (as far as I have deducted).   

Doesn't Intel have a common method to follow all the way through from generating programming files to actually programming their devices somewhere that I just haven't found despite a rather extensive search?

If you have any information that could help this apparent ignoramus, I would be most grateful.

Thanks in advance! 

[aikeu]

Hi Badeskov,

May I know you are building Arria10 or Cyclone V?

Are you having problem preparing the sd card image?

For WSL some of the packages will need to be installed:

 a. sudo apt update

b. sudo apt install wsl

 c. sudo apt install dos2unix

 d. sudo apt install make  

 e. sudo apt install build-essential

Example link:

https://www.intel.com/content/www/us/en/support/programmable/articles/000074066.html

Thanks.

Regards,

Aik Eu

[Badeskov]

Hi Aik,

Thank you very much for your reply. To answer your questions, I'm building towards Cyclone V and, yes, it is the SD image that troubles me. Or, rather, the lack on continuity in documentation from project start to end. I did all the initial parts as per the Intel and Windows documentation and build the prerequisites as per the Rocketboards instructions. 

Install/enable WSL1 with Ubuntu 18.04 (every document I found from Intel specifically mentions this, as the debug is allegedly not compatible with WSL2). That includes the apt installs you mention. That works just fine, and I tested that I could generate the compile files just fine, even the .sof though I prefer to do that directly from Quartus. Thus far all is good, albeit cumbersome.

Then comes the conundrum, the generation of the SD image. That apparently requires WSL2, in particular the bitbake (Yocto),  which obviously contradicts the Intel requirement of using WSL1. So then what? I have also tried these instructions from Intel on creating the SD image:

https://www.intel.com/content/www/us/en/docs/programmable/683435/17-1/creating-an-sd-flash-card-image.html

And then we get back to WSL1 versus WSL2. Since WSL1 is not true virtualization, the instructions fail, or at least they did for me. 

So, I guess my true complaint is the lack of a thorough, continuous and complete guide line from Intel from beginning to end with all the instructions and requirements listed so even a process engineer could sit down and do this if given all the FPGA files. Instead, a search on various, disparate boards is required to fix all the problems/missing installs etc. that crops up along the way and that are simply not documented in any way, shape or form. I could understand the lack of documentation should I be trying something the FPGA/SoC was not intended for, but this is the main purpose of this part that I am trying to implement and the lack of coherent documentation on this from Intel's side is honestly outright baffling to me.

I don't mind learning, but continuously wasting my time on something that should have been properly documented and apparently, over the years, consistently was not is something I truly hate.    

[aikeu]

Hi Badeskov,

Sorry for the inconvinience, I will take note on your feedback regarding the process to setup the build environment in Windows.

Normally for SoC build, most build process were tested with Linux base OS as the process has more dependencies with linux environment. For my case I normally work with Ubuntu.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Badeskov,

I will close this thread if no further question.

Thanks.

Regards,

Aik Eu