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Quartus P-Tile PCIe IP config crashes

jmcguire3
Novice
3,310 Views

Trying to configure a basic PCIe interface on the Agilex F014 EVM, and the P-Tile IP configuration crashes if I disable either the read-data-mover or write-data-mover functions under the Avalon-MM Settings tab.  Re-enabling the data-mover button leaves the configurator in a persistently confused state.  Something bad is happening during core elaboration.  

 

I don't have a streaming-data application, so the ST core isn't useful.  I don't have any DMA support in my system (hence the desire to disable the data-movers.)  

 

This issue exists in Quartus 22.3 and 22.4.  We have a system with PCIe-to-Avalon-MM running on a Cyclone 10GX and it works fine.  We want to have comparable functionality on our Agilex-based boards, but the P-Tile core appears to be broken.  Screen shot and error log are attached.

 

 

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wchiah
Employee
2,586 Views

Hi,


May I know why you disable those features ?

is there any unavoided specific reason doing that ?


Regards,

Wei Chuan


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wchiah
Employee
2,565 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

 

Regards,

Wincent_Intel


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jmcguire3
Novice
2,554 Views

I am working with multiple platforms that have PCIe interconnect as the only available control-plane interaction.  These are deployed systems, so a design constraint is to use the existing memory-mapped PCIe control paradigm.  The host controller sets operating parameters via memory-mapped port writes, reads machine status via port reads, responds to interrupts on the various cards, and blinks LEDs ... you know, normal hardware-system tasks.  The target cards are big state machines with no local processor.

The system does not operate with DMA-anything.  We are not transferring blocks of data in a packet/protocol structure.  We disabled the DMA data movers because they have zero place in our system architecture.  We just need memory-mapped control ports, and legacy interrupts to trigger event responses.  We have these operational with Stratix 10 and Cyclone 10 FPGAs, and they work fine.  We are migrating to an Agilex-based design, and that's where we bashed into the P-Tile support issue.  Functionally, the P-Tile should be able to handle a memory-mapped Avalon interface.

We found this bit in the documentation disturbing -

Note: Do not use the P-tile Avalon® Memory-mapped IP for PCI Express* for new designs. This IP will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP.

(ref: https://www.intel.com/content/www/us/en/docs/programmable/683853/21-1-4-0-0/design-example-overview.html )

Not sure why Intel/Altera would think that there's no place for direct-mapped port-I/O construct in a hardware-based platform ... 

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wchiah
Employee
2,511 Views

Hi,

 

I did a double-check on that, what wroten in the user is correct.

If you believe your business case justifies that Intel should invest in providing P-tile Avalon® Memory-mapped IP for PCI Express*

My suggestion will be please work directly with your cognizant Sales/FAE to submit this feature request.

 

Regards,

Wincent_Intel

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jmcguire3
Novice
2,496 Views

Thank you for verifying.

Not sure how we are going to proceed.  Intel's recommendation to use the Multi-Channel DMA IP for memory-mapped applications doesn't appear to be a workable solution - legacy MSI interrupts aren't supported, and MSI-X interrupts appear to be broken as far back as 22.1 ... seems you're SOL if you need interrupt support across the PCIe connection.


The following summarizes known issues in the current IP release [v22.1]:

  1. Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the User MSI-X feature in the Multi Channel DMA Intel FPGA IP for PCI Express is not functional.

https://www.intel.com/content/www/us/en/docs/programmable/683821/22-1/known-issues.html

 

Explains why the MSI-X radio button and subtended selections in Quartus are not-selectable.

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wchiah
Employee
2,464 Views

Hi,

I dont get your question, is there any relationship between MSI-X feature and  read-data-mover or write-data-mover functions under the Avalon-MM Settings tab that you mention early ?

Regards,

Wincent_Intel

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jmcguire3
Novice
2,448 Views

Intel is deprecating the PCIe Avalon-MM IP core, and recommends not-using it in new designs.  (Post #4, above.)  In the immediately following sentence, Intel recommends that customers should use the MCDMA core instead.  I explored the possibility of using it.

My application performs reads and writes to memory-mapped ports in response to interrupts from the target device.  Think "closed loop feedback machine control" and not "streaming cat videos."  We currently implement interrupt support via the legacy MSI functions.  Our host system is running an interrupt-driven executive.

The MCDMA IP core does not appear to support MSI.  However there is an MSI-X tab, which suggests that interrupts could be implemented via the message-based construct, albeit with a substantial increase in level-of-effort to do so.  Unfortunately, MSI-X support appears to be "not functional."  Intel's recommended "use the MCDMA core" is only a solution for a subset of the customer base who don't use interrupts ... 

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wchiah
Employee
2,380 Views

Hi,


Please apologies for the inconvenience cause to you due to the features missmatch.

Is there anything you think I can help you on that ?


Regards,

Wincent_intel


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jmcguire3
Novice
2,370 Views

Well, I thought I would try to work within the system rather than fight it.  Opened a new, clean design and instantiated the PCIe Avalon-MM IP core.  My thought process - leave the existing DMA / memory-mover construct in place, and just spackle-on an I/O port construct. 

 

Found that making any change to a parameter crashes the elaborator script.  The attached screen grab shows the result of changing only the Revision ID field ... you know, something that you would want to update when you change the contents of the design.  Tested this in both 22.3 and 22.4 versions of Quartus Pro.

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wchiah
Employee
2,346 Views

Hi,


Is there anything else you think I can help/clarified more ?


Regards,

Wincent_Intel


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jmcguire3
Novice
2,315 Views

That's a very bot-like reply, though it's probably a hot-key-mapped scripted response.  Likely, your hand is hovering over the key to issue:

  • We have not hear from you and this Case is idling. It is not recommended to idle for too long.
  • Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause
  • Hence, This thread will be transitioned to community support.

You've verified that the problem exists, but "talk to your sales rep" isn't much "help."

If you're inclined to punt this into Community Support mode, you'll need to publish the P-Tile API so we community members can do something with it.  The P-Tile lives between the FPGA fabric and the PCIe pins, so we can't bypass the P-Tile with a custom design.

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wchiah
Employee
2,306 Views

Hi,

Please accept my apologies for any inconvenience caused to you.
As all the spec is mentioned in the user guide, there might have some limitation on it.
If the MSI-X feature is important for you in the MCDMA mode, I will help to submit an internal ticket on the feature request.
Hope the team will consider to include it in the future release version of software.

Is there anything else you think I can assist you better ? Please let me know

Regards,

Wincent_Intel

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jmcguire3
Novice
2,245 Views

All things being equal, I'd rather that Intel/Altera would fix the bug(s) in the PCIe Avalon-MM IP core and not discontinue it.  I find it difficult to believe that I'm the only engineer on the planet who wants to be able to poke memory locations and respond to peripheral interrupts via PCIe.

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wchiah
Employee
2,208 Views

Hi,


I understand your concern. I had submit an internal ticket for this features request.

Is there anything else you think I can better support you ?


Regards,

Wincent_Intel


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wchiah
Employee
2,189 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

or there is anything you think I can help you more ?

 

Regards,

Wincent_Intel


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wchiah
Employee
2,175 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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jmcguire3
Novice
2,162 Views

Wow, it's a carbon-copy from my post on 2/21.  Is that <Alt><F3> or <Alt><F5>?  (or more likely one followed by the other?)

 

Two days "idling", then scraped off your shoe.  Nice.  Nothing says "please go away" like being transitioned to community support.

 

The demo design included with the PCIe Avalon-MM core produces a Platform Designer entry that has a "generic component" instead of the PCIe core proper.  This Generic Component appears to have all of the 2000-ish P-Tile parameters unrolled as a flat file (further evidence that Intel/Altera knows the PCIe Avalon-MM core generator is broken.)  While no doubt comprehensive, this is not particularly useful unless you have the P-Tile API document that describes all of the various parameters and their inter-relationships.  Any chance Intel/Altera can publish the API so we, the community, can move forward?  The P-Tile hardware supports the Avalon-MM interface.  The script generating the parameters is broken.  Intel/Altera doesn't want to support it.  Give me the ability to fix it myself.

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wchiah
Employee
2,141 Views

Hi,

 

I understand your concern, I will remain this as open until you got a satisfies answer.
Please allow me to continue support you on your request, if you feel anything that I can help you to move on, please do not hesitate to let me know.

 

If you need P-tile API flow and list, you can get it at link below.

Regards, 
Wincent_Intel

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jmcguire3
Novice
2,083 Views

Those APIs are for software development/support of the interface.  We, the community, would need access to the hardware APIs that define configurations and interconnects across the AIB/EMIB boundary.  We have a copy of the AIB 1.2 spec, and that's clearly a physical interface definition to connect the FPGA core to the P-Tile chiplet.  The API we need would define the P-Tile parameters and the hardware configuration method for the chiplet at the hardware-reset level ... that should happen waaay before software gets involved.  Presumably we can come forward with the same system architecture as found in the factory-included example design, where Intel/Altera implements the Avalon-MM IP core as a "generic component" and just unrolls the 2000-ish parameters as a long flat list. 

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wchiah
Employee
2,097 Views

Hi,


Did the information enough for you ?

Let me know if there is anything I can help you.


Regards,

Wincent_Intel


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