Quartus PLL - How to connect to existing VHDL

[Altera_Forum]

Hi! 

 I try to use the PLL function the first time and have some problems with it. It would be great if anyone could help me.  I used the MegaWizard PlugIn Manager to specify the PLL settings. But now I can't find out how to "connect" it with my existing VHDL program. I am using a Clk signal named "Osc" and I want to connect it to the PLL inclk0. Furthermore I need a Process with should reacts on the c0 PLL out.  I tried the following but I get the message "Error (10482): VHDL error at BX48.vhd(396): object "c0" is used but not declared". How can I access the c0 output from the PLL?  TestProcess: process (c0)   begin   if c0'Event and co = '1' then  --Todo...  end if;  end process TestProcess;  Details: Quartus 9.1, Cyclone III  Regards Andre

[Altera_Forum]

You have to instantiate the PLL MegaFunction as a component in your design. The Megawizard generates a component definition and an instantiation template by default. Both parts can be copied to your design.

[Altera_Forum]

I have instantiate the PLL MegaFunction already. There is a PLL.vhd in the directory. But I don't know how I can access it from my main VHDL file. 

 Sorry for the stupid question, but I am a VHDL newby. I used only a single VDHL file until now...

[Altera_Forum]

Ok, I tried to instiate the component in my design. But I get the error message "Error (10482): VHDL error at BX48.vhd(392): object "altpll" is used but not declared". 

 I wrote the following code into the architecture area after "begin":  i_cyclonepll : altpll  port map (  areset => Pll_areset,  configupdate => Pll_configupdate,  inclk0 => Pll_inclk0,  scanclk => Pll_scanclk,  scanclkena => Pll_scanclkena,  scandata => Pll_scandata,  c0 => Pll_c0,  locked => Pll_locked,  scandataout => Pll_scandataout,  scandone => Pll_scandone);  Regards, Andre

[Altera_Forum]

No problem. If you insert the MegaWizard generated instantiation template, you have this code in your architecture body.  

pll1_inst : pll1 PORT MAP ( areset => areset_sig, inclk0 => inclk0_sig, c0 => c0_sig, locked => locked_sig );  areset and locked are optional signals enabled by default, you don't need them most likely. inclk0_sig should be connected to your clock (you can place the input port signal on the right side of the assignment directly) and c0_sig is your PLL generated clock. Of course, the signal must be defined in the architecture.

[Altera_Forum]

Thanks for your help! 

 Now I get the error message "Error (10482): VHDL error at BX48.vhd(392): object "pll1" is used but not declared".  ?!

[Altera_Forum]

Where can I find the instantiation template? There is no file with the extension _inst.vhd in the project directory.

[Altera_Forum]

Ok, I just found out that there is an optional checkbox in the wizard for generating the _inst.vhd.

[Altera_Forum]

I copied the content from the _inst.vhd into my VHDL file. But I get the same error message "Error (10482): VHDL error at BX48.vhd(407): object "PLL" is used but not declared"... 

 PLL_inst : PLL PORT MAP (  areset => areset_sig,  configupdate => configupdate_sig,  inclk0 => Osc,  scanclk => scanclk_sig,  scanclkena => scanclkena_sig,  scandata => scandata_sig,  c0 => c0_sig,  locked => locked_sig,  scandataout => scandataout_sig,  scandone => scandone_sig  );

[Altera_Forum]

The component name specified in the MegaWizard must match the component name used in the declarative part of the architecture. As I previously mentioned, both component definition and and instantiation template generated by the Megawizard should be copied. 

 I'm sure, that you can figure out the right method by "trial and error". A VHDL text book or tutorial could be a shortcut, I think.

[Altera_Forum]

Assuming you're set for VHDL 1993 compilation (the default) you dont need a component declaration at all. Use this method instead: 

  pll1_inst : entity work.pll1 PORT MAP ( areset => areset_sig, inclk0 => inclk0_sig, c0 => c0_sig, locked => locked_sig );  This method looks for the entity in the source file instead (make sure the pll1 source file is included in the project).

[Altera_Forum]

Thank you very much to you all! 

 The problem was that I didn't wrote the component specification into the declarative part of my architecture. I thought it is adequate enough if it is written in the generated pll file.  The tip from "tricky" without the component specification works also. And it makes it even better in my eyes (no redundant specification).  Regards, Andre

[Altera_Forum]

--- Quote Start ---   The tip from "tricky" without the component specification works also. And it makes it even better in my eyes (no redundant specification).   --- Quote End ---    The great thing about this method is you dont have to wait until synthesis to find theres a missmatch between the component and the entity declaration; the compiler will pick it up really quick. Its quite easy to modify an entity and forget to update the component declaration - especially when you use it in several different files.