Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus Partition Merge Usage ?? What is the good and bad if turn it off?

Altera_Forum
Honored Contributor II
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Hi, 

 

Anyone knows what is the usage of partition merge in quartus cad flow. From the definition in quartus handbook chapter 3 "quartus ii incremental compilation for hierarchical and team-based design",  

 

"partition merge stage The Partition Merge step creates a single, complete netlist that consists of post-synthesis netlists, post-fit 

netlists, and netlists exported from other Quartus II projects, depending on the netlist type that you specify 

for each partition." 

 

It seems like it only speed up the fitter process by reuse-ing the previous post-fit netlist. Is that correct? It didn't do any resource sharing during this stage? 

 

Thanks, 

OT
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Altera_Forum
Honored Contributor II
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You are correct. The idea is to have completed sections of the FPGA saved in partitions so that they don't need to be fitted every time the configuration is built. If you have a timing sensitive design partition that has already been verified, that verification doesn't need to be redone.

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Altera_Forum
Honored Contributor II
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I see. Thanks for the clarification, Galfonz. :)

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