Quartus Prime 16.1 Lite compilation issue

Altera_Forum · ‎04-03-2017

Hi All,

I met a problem that my software cannot generate an 500ms counter, see my code and picture, can you help me?

https://alteraforum.com/forum/attachment.php?attachmentid=13466&stc=1


/********************Test01***********************
Project Name: Test01;
Function: Just test my FPGA board
Version: 0.1
Editor: Vincent Li
Date: 2017-04-03
clk=50MHz
*************************************************/
module test01( clk, nRST, LED	);
input clk,nRST;
output LED;
parameter T500MS = 25'd24_999_999;
reg rLED;
reg Count;
			
always@(posedge clk or negedge nRST)
	if(!nRST)
		Count <= 25'd0;
		else
			Count <= Count + 1'b1;
			
always@(posedge clk or negedge nRST)
	if(!nRST)
		rLED <= 4'd1;
		else if(T500MS==25'd24_999_999)
			rLED <= {rLED,rLED};
				
assign LED = rLED;
				
								
endmodule

Altera_Forum · ‎04-03-2017

Here is the problem:

else if(T500MS==25'd24_999_999)

This is always true - I think you meant count?

Altera_Forum · ‎04-04-2017

Hi Tricky,

thank you for your reply, yes you are correct...I had corrected this morning and it works.

Br