I'm using a Cyclone V and trying to pass through an HD-SDI signal from a GXB Rx pin -through the FPGA- to a GXB Tx pin. They are on the same Bank. I am new to the SDI protocol and would like some tips on how much of the IP core do I have to use in order to passively connect this input to output signal.
Is it possible to instantiate just one module of SDI_ii as a bidirectional unit and then wrap the Rx lines to the Tx lines? Or would it be easier to instantiate one module of SDI_ii as a receiver and one module of SDI_ii as a transmitter?
Per my understanding from your description, you want to implement SDI-SDI loopback.
The SDI II duplex loopback example design for Cyclone V GT is available below for reference.
This Design Example SDI II IP design support loopback.