Quartus Prime Lite 20.1 reports a compile error on valid systemverilog generate block syntax

[gchadwick]

The following system verilog produces an error in Quartus Prime Lite 20.1:

logic [7:0] foo;

for (genvar i = 0;i < 8; i++) begin : g_test
  assign foo[i] = 1'b0;
end

The error seen is:

Error (10170): Verilog HDL syntax error at top.v(258) near text: "for";  expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

It is valid system verilog accepted by a wide range of other tools.

Adding explicit generate/endgenerate doesn't fix it entirely:

logic [7:0] foo;

generate
  for (genvar i = 0;i < 8; i++) begin : g_test
    assign foo[i] = 1'b0;
  end
endgenerate

As it doesn't like the genvar declaration within the for loop:

Error (10170): Verilog HDL syntax error at top.v(259) near text: "genvar";  expecting an identifier ("genvar" is a reserved keyword ). Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Again this is valid system verilog syntax

The following version will successfully compile:

logic [7:0] foo;

generate
  genvar i;
  for (i = 0;i < 8; i++) begin : g_test
    assign foo[i] = 1'b0;
  end
endgenerate

Is there a way to report this to Intel beyond posting in these forums? Whilst you can work around it this can make it hard to work with RTL that's already written as you need to manually fix it to build it with Quartus Prime Lite.

[sstrell]

Just to verify, in the project settings, which version of Verilog have you selected for the compilation (under compiler settings)?  Perhaps you have it set to an older compiler version that is causing the issue.

#iwork4intel

[gchadwick]

The language version is set to system verilog (under Assignments->Settings->Compiler Setting->Verilog HDL Input)